9DBV0631BKLF Datasheet 9DBV0631BKLF, 9DBV0631BKILF | P7-P9

REVISION H 07/27/16 7 6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB

9DBV0631 DATASHEET

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

Conditions

TA = T

AMB

, Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Supply Volta

e VDDx Supply volta

e for core and analo

1.7 1.8 1.9 V

Output Supply Volta

e VDDIO Supply volta

e for Low Power HCSL Outputs 0.95 1.05-1.8 1.9 V

Commmercial range 0 25 70 °C

Industrial range -40 25 85 °C

Input High Voltage V

Single-ended inputs, except SMBus 0.75 V

+ 0.3 V

Input Mid Voltage V

Single-ended tri-level inputs ('_tri' suffix) 0.4 V

0.6 V

Input Low Voltage V

Single-ended inputs, except SMBus -0.3 0.25 V

Single-ended inputs, V

= GND, V

= VDD -5 5 uA

INP

Single-ended inputs

= 0 V; Inputs with internal pull-up resistors

= VDD; Inputs with internal pull-down resistors

-200 200 uA

Bypass mode 1 200 MHz 2

100MHz PLL mode 50 100.00 140 MHz 2

125MHz PLL mode 62.5 125.00 175 MHz 2

50MHz PLL mode 25 50.00 65 MHz 2

Pin Inductance L

7nH1

Logic Inputs, except DIF_IN 1.5 5 pF 1

INDIF_IN

DIF_IN differential clock inputs 1.5 2.7 pF 1,6

OUT

Output pin capacitance 6 pF 1

Clk Stabilization T

STAB

From V

Power-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

1ms1,2

Input SS Modulation

Frequency PCIe

MODI NPCI e

Allowable Frequency for PCIe Applications

(Trian

ular Modulation)

30 33 kHz

Input SS Modulation

Frequency non-PCIe

MODI N

Allowable Frequency for non-PCIe Applications

(Trian

ular Modulation)

066kHz

OE# Latency t

LATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

1 3 clocks 1,3

Tdrive_PD# t

DRVPD

DIF output enable after

PD# de-assertion

300 us 1,3

Tfall t

Fall time of single-ended control inputs 5 ns 2

Trise t

Rise time of single-ended control inputs 5 ns 2

SMBus Input Low Voltage V

ILSMB

DDSMB

= 3.3V, see note 4 for V

DDSMB

< 3.3V 0.8 V 4

SMBus Input High Voltage V

IHSMB

DDSMB

= 3.3V, see note 5 for V

DDSMB

< 3.3V 2.1 3.6 V 5

SMBus Output Low Voltage V

OLSMB

@ I

PULLUP

0.4 V

SMBus Sink Current I

PULLUP

@ V

4mA

Nominal Bus Voltage V

DDSMB

Bus Voltage 1.7 3.6 V

SCLK/SDATA Rise Time t

RSMB

(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1

SCLK/SDATA Fall Time t

FSMB

(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1

SMBus Operating

Frequency

MAXSMB

Maximum SMBus operating frequency 400 kHz 7

Guaranteed by desi

n and characterization, not 100% tested in production.

Control input must be monotonic from 20% to 80% of input swin

Ambient Operating

Temperature

AMB

Input Current

Input Frequency

Capacitance

Time from deassertion until outputs are >200 mV

For V

DDSMB

< 3.3V, V

ILSMB

<= 0.35V

DDSMB

For V

DDSMB

< 3.3V, V

IHSMB

>= 0.65V

DDSMB

DIF_IN input

The differential input clock must be running for the SMBus to be active

6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB 8 REVISION H 07/27/16

9DBV0631 DATASHEET

Electrical Characteristics–Low-Power HCSL Outputs

Electrical Characteristics–Current Consumption

TA = T

AMB

; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

dV/dt Scope averaging on, fast setting 1.7 2.9 4

V/ns

1,2,3

dV/dt Scope averaging on, slow setting 1.1 2.1 3.4

V/ns

1,2,3

Slew rate matching



dV/dt Slew rate matching, Scope averaging on 7 20

1,2,4

Voltage High V

HIGH

660 774 850 7

Voltage Low V

LOW

-150 18 150 7

Max Voltage Vmax 821 1150 7

Min Voltage Vmin -300 -15 7

Vswing Vswing Scope averaging off 300 1536 mV 1,2

Crossing Voltage (abs) Vcross_abs Scope averaging off 250 414 550 mV 1,5

Crossing Voltage (var)

-Vcross Scope averaging off 13 140 mV 1,6

Measured from differential waveform

At default SMBus settings.

Slew rate

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

Measurement on single ended signal using

absolute value. (Scope averaging off)

Guaranteed by design and characterization, not 100% tested in production.

Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on

the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations.

Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross

absolute) allowed. The intent is to limit Vcross induced modulation by setting

-Vcross to be smaller than Vcross absolute.

TA = T

AMB

; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

DDA

VDDA+VDDR, PLL Mode, @100MHz

11 15

mA 1

VDD, All outputs active @100MHz

610

mA 1

DDO

VDDIO, All outputs active @100MHz

24 30

mA 1

DDAPD

VDDA+VDDR, CKPWRGD_PD#=0

0.4 0.6 mA 1, 2

DDPD

VDD, CKPWRGD_PD#=0 0.5 0.8 mA 1, 2

DDOPD

VDDIO, CKPWRGD_PD#=0 0.0003 0.1 mA 1, 2

Guaranteed by design and characterization, not 100% tested in production.

Input clock stopped.

Operating Supply Current

Powerdown Current

REVISION H 07/27/16 9 6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB

9DBV0631 DATASHEET

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

Electrical Characteristics–Phase Jitter Parameters

TA = T

AMB

; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

-3dB point in High BW Mode

1.8 2.7 3.8

MHz 1,5

-3dB point in Low BW Mode

0.8 1.4 2

MHz 1,5

PLL Jitter Peaking t

JPEAK

Peak Pass band Gain

1.1 2

dB 1

Duty Cycle t

Measured differentially, PLL Mode 45

50.1

55 % 1

Duty Cycle Distortion t

DCD

Measured differentially, Bypass Mode @100MHz -1

0.0

1%1,3

dBYP

Bypass Mode, V

= 50% 3000

3636

4500 ps 1

dPLL

PLL Mode V

= 50% 0

200 ps 1,4

Skew, Output to Output t

sk3

= 50%

50 ps 1,4

PLL mode

50 ps 1,2

Additive Jitter in Bypass Mode

0.1

5ps1,2

Guaranteed by design and characterization, not 100% tested in production.

Measured from differential waveform

Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

All outputs at default slew rate

The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.

Skew, Input to Output

Jitter, Cycle to cycle t

jcyc-cyc

PLL Bandwidth BW

TA = T

AMB

; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions

PARAMETER SYMBOL CONDITIONS MIN TYP MAX

INDUSTRY

LIMIT UNITS Notes

hPCIeG1

PCIe Gen 1 31 52 86 ps (p-p) 1,2,3,5

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.8 1.4 3

(rms)

1,2,3,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2.3 2.5

3.1

(rms)

1,2,3,5

jphPCIeG3

PCIe Gen 3 Common Clock Architecture

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.5 0.6

(rms)

1,2,3,5

jphPCIeG3SRn

PCIe Gen 3 Separate Reference No Spread (SRnS)

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.5 0.6

0.7

(rms)

1,2,3,5

jphSGMII

125MHz, 1.5MHz to 20MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

1.9

2N/A

(rms)

1,2,3,5

jphPCIeG1

PCIe Gen 1 0.1 5 N/A

(p-p)

1,2,3

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.1 0.4 N/A

(rms)

1,2,5

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.10 0.3 N/A

(rms)

1,2,5

jphPCIeG3

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.00 0.1 N/A

(rms)

1,2,4,5

jphSGMIIM0

125MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

165 200 N/A

(rms)

1,6

jphSGMIIM1

125MHz, 12kHz to 20MHz, -20dB/decade rollover

< 1.5MHz, -40db/decade rolloff > 10MHz

251 300 N/A

(rms)

1,6

Guaranteed by design and characterization, not 100% tested in production.

For RMS fi

ures, additive jitter is calculated by solvin

the followin

equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

Driven by 9FGV0831 or equivalent

Rohde&Schartz SMA100

Additive Phase Jitter

jphPCIeG2

See htt

://www.

cisi

.com for com

lete s

ecs

Sam

le size of at least 100K c

cles. This fi

ures extra

olates to 108

k @ 1M c

cles for a BER of 1-12.

Phase Jitter, PLL Mode

jphPCIeG2

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

9DBV0631BKLF

Mfr. #:

Buy 9DBV0631BKLF

Manufacturer:

IDT

Description:

Clock Buffer 6-output 1.8 V PCIe Gen1-2-3 Zero-Delay

Lifecycle:

New from this manufacturer.

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9DBV0631BKLF

9DBV0631BKLF

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