6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB 16 REVISION H 07/27/16
9DBV0631 DATASHEET
Revision History
Rev. Intiator Issue Date Description Page #
A RDW 9/5/2012
1. Pinout changed from 48 to 40 pins. Paddle is now GND
2. Thermal data added
3. General Description/Front Page Text updated to match other
9DBVxx31 devices.
4. SMBus updated.
5. Power Ground Connections updated.
6. Electrical tables updated.
7. Move to preliminary.
Various
B RDW 9/17/2012 1. Changed ordering information from 9DBV0631A to 9DBV0631B
C RDW 2/25/2013
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to
0.6*VDD.
6
D S.L. 7/7/2014 Updated top-side deive marking and associated notes. 12
E RDW 9/10/2014
1. Updated front page text for consistency.
2. Updated block diagram for consistency.
3. Updated electrical tables with characterization data.
4. Updated SMBus nomenclature - bits did NOT change.
5. Converted to new doc template.
6. Changed IDD spec from 8mA to 10mA MAX.
Various
F RDW 11/7/2014 1. Widened input frequency ranges for PLL modes. 7
G RDW 4/28/2016
1. Updated max frequency of 100MHz PLL mode to 140MHz
2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
7
H RDW 7/27/2016
Corrected ordering information typo by adding “T” for Tape and Reel
devices.
15
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9DBV0631BKLF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 6-output 1.8 V PCIe Gen1-2-3 Zero-Delay
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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