CS5521-ASZ Datasheet CS5524-ASZ, CS5523-ASZ, CS5528-ASZ | P1-P3

http://www.cirrus.com

CS5521/22/23/24/28

16-bit or 24-bit, 2/4/8-channel ADCs with PGIA

Features

 Low Input Current (100 pA), Chopper-

stabilized Instrumentation Amplifier

 Scalable Input Span (Bipolar/Unipolar)

- 2.5V VREF: 25 mV, 55 mV, 100 mV, 1 V,

2.5 V, 5 V

- External: 10 V, 100 V

 Wide V

REF

Input Range (+1 to +5 V)

 Fourth Order Delta-Sigma A/D Converter

 Easy to Use Three-wire Serial Interface Port

- Programmable/Auto Channel Sequencer with

Conversion Data FIFO

- Accessible Calibration Registers per Channel

- Compatible with SPI™

and Microwire™

 System and Self Calibration

 Eight Selectable Word Rates

- Up to 617 Sps (XIN = 200 kHz)

- Single Conversion Settling

- 50/60 Hz ±3 Hz Simultaneous Rejection

 Single +5 V Power Supply Operation

- Charge Pump Drive for Negative Supply

- +3 to +5 V Digital Supply Operation

 Low Power Consumption: 6.0 mW

General Description

The CS5521/22/23/24/28 are highly integrated ΔΣ ana-

log-to-digital converters (ADCs) which use charge-

balance techniques to achieve 16-bit (CS5521/23) and

24-bit (CS5522/24/28) performance. The ADCs

come as

either two-channel (CS5521/22), four-channel

(CS5523/24), or eight-channel (CS5528) devices and

include a low-input-current, chopper-stabilized instru-

mentation amplifier. To permit selectable input spans of

25 mV, 55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs

include a PGA (programmable gain amplifier). To ac-

commodate ground-based thermocouple applications,

the devices include a charge pump drive which provides

a negative bias voltage to the on-chip amplifiers.

These devices also include a fourth-order ΔΣ modulator

followed by a digital filter

which provides eight selectable

output word rates

. The digital filters are designed to settle

to full accuracy within one conversion cycle and when

operated at word rates below 30 Sps, they reject both

50 Hz and 60 Hz interference.

These single-supply products are ideal solutions for

measuring isolated and non-isolated, low-level signals in

process control applications.

ORDERING INFORMATION

See page 53.

VA+ AGND VREF+ VREF- VD+DGND

XIN XOUT

NBV

Latch

Differential

Digital Filter

Order

ΔΣ

Modulator

Clock

Gen.

MUX

AIN2+

CS5524

Shown

AIN2-

AIN1+

AIN1-

AIN4+

AIN4-

AIN3+

AIN3-

A0 A1CPD

Controller,

Programmable

Gain

Setup Registers,

Data FIFO &

Calibration Registers

Channel Scan

Logic

Serial Port

Interface

X20

SDO

SDI

SCLK

JUL ‘09

DS317F8

CS5521/22/23/24/28

2 DS317F8

TABLE OF CONTENTS

ANALOG CHARACTERISTICS................................................................................................ 5

TYPICAL RMS NOISE, CS5521/23.......................................................................................... 7

TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 .................................................... 7

TYPICAL RMS NOISE, CS5522/24/28..................................................................................... 8

TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 ............................................... 8

5 V DIGITAL CHARACTERISTICS........................................................................................... 9

3 V DIGITAL CHARACTERISTICS........................................................................................... 9

DYNAMIC CHARACTERISTICS ............................................................................................ 10

RECOMMENDED OPERATING CONDITIONS ..................................................................... 10

ABSOLUTE MAXIMUM RATINGS ......................................................................................... 10

SWITCHING CHARACTERISTICS ........................................................................................ 11

1. GENERAL DESCRIPTION ..................................................................................................... 13

1.1 Analog Input ..................................................................................................................... 13

1.1.1 Instrumentation Amplifier .........................................................................................14

1.1.2 Coarse/Fine Charge Buffers ............................................................................... 14

1.1.3 Analog Input Span Considerations ..........................................................................15

1.1.4 Measuring Voltages Higher than 5 V .................................................................. 15

1.1.5 Voltage Reference .............................................................................................. 16

1.2 Overview of ADC Register Structure and Operating Modes ............................................ 16

1.2.1 System Initialization ............................................................................................ 18

1.2.2 Command Register Quick Reference ............................................................... 19

1.2.3 Command Register Descriptions ........................................................................ 20

1.2.4 Serial Port Interface ............................................................................................ 25

1.2.5 Reading/Writing the Offset, Gain, and Configuration Registers ..........................26

1.2.6 Reading/Writing the Channel-Setup Registers ................................................... 26

1.2.6.1 Latch Outputs ...................................................................................... 28

1.2.6.2 Channel Select Bits ............................................................................. 28

1.2.6.3 Output Word Rate Selection ............................................................... 28

1.2.6.4 Gain Bits .............................................................................................. 28

1.2.6.5 Unipolar/Bipolar Bit ............................................................................. 28

1.2.7 Configuration Register ........................................................................................ 28

1.2.7.1 Chop Frequency Select ....................................................................... 28

1.2.7.2 Conversion/Calibration Control Bits .................................................... 28

1.2.7.3 Power Consumption Control Bits ........................................................ 28

1.2.7.4 Charge Pump Disable ......................................................................... 29

1.2.7.5 Reset System Control Bits .................................................................. 29

1.2.7.6 Data Conversion Error Flags ............................................................... 29

1.3 Calibration ........................................................................................................................ 31

1.3.1 Self Calibration .................................................................................................... 31

1.3.2 System Calibration .............................................................................................. 32

1.3.3 Calibration Tips ................................................................................................... 34

1.3.4 Limitations in Calibration Range ......................................................................... 34

1.4 Performing Conversions and Reading the Data Conversion FIFO .................................. 34

1.4.1 Conversion Protocol ............................................................................................ 35

1.4.1.1 Single, One-Setup Conversion ............................................................ 35

1.4.1.2 Repeated One-Setup Conversions without Wait ................................. 35

1.4.1.3 Repeated One-Setup Conversions with Wait ...................................... 36

1.4.1.4 Single, Multiple-Setup Conversions .................................................... 36

1.4.1.5 Repeated Multiple-Setup Conversions without Wait ........................... 37

1.4.1.6 Repeated Multiple-Setup Conversions with Wait ................................ 37

1.4.2 Calibration Protocol ............................................................................................. 38

CS5521/22/23/24/28

DS317F8 3

1.4.3 Example of Using the CSRs to Perform Conversions and Calibrations .............. 38

1.5 Conversion Output Coding .............................................................................................. 40

1.5.1 Conversion Data FIFO Descriptions ................................................................... 41

1.6 Digital Filter ..................................................................................................................... 42

1.7 Clock Generator .............................................................................................................. 42

1.8 Power Supply Arrangements ........................................................................................... 43

1.8.1 Charge Pump Drive Circuits ............................................................................... 45

1.9 Digital Gain Scaling ........................................................................................................ 45

1.10 Getting Started .............................................................................................................. 46

1.11 PCB Layout ................................................................................................................... 48

2. PIN DESCRIPTIONS .............................................................................................................. 49

2.1 Clock Generator .............................................................................................................. 50

2.2 Control Pins and Serial Data I/O ..................................................................................... 50

2.3 Measurement and Reference Inputs ............................................................................... 50

2.4 Power Supply Connections ............................................................................................. 51

3. SPECIFICATION DEFINITIONS ............................................................................................. 52

4. ORDERING INFORMATION .................................................................................................. 53

5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 53

6. PACKAGE DIMENSION DRAWINGS .................................................................................... 54

7. REVISION HISTORY .............................................................................................................. 56

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P56

CS5521-ASZ

Mfr. #:

Buy CS5521-ASZ

Manufacturer:

Cirrus Logic

Description:

Analog to Digital Converters - ADC 2-Ch 16-Bit Delta Sigma ADC

Lifecycle:

New from this manufacturer.

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CS5521-ASZ

CS5521-ASZ

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