CS5521-ASZ Datasheet CS5524-ASZ, CS5523-ASZ, CS5528-ASZ | P13-P15

CS5521/22/23/24/28

DS317F8 13

1. GENERAL DESCRIPTION

The CS5521/22/23/24/28 are highly integrated ΔΣ

Analog-to-Digital Converters (ADCs) which use

charge-balance techniques to achieve 16-bit

(CS5521/23) and 24-bit (CS5522/24/28) perfor-

mance. The ADCs

come as either two-channel

(CS5521/22), four-channel (CS5523/24), or eight-

channel (CS5528) devices, and include a low input

current, chopper-stabilized instrumentation ampli-

fier. To permit selectable input spans of 25 mV,

55 mV, 100 mV, 1 V, 2.5 V, and 5 V, the ADCs in-

clude a PGA (programmable gain amplifier). To

accommodate ground-based thermocouple applica-

tions, the devices include a CPD (Charge Pump

Drive) which provides a negative bias voltage to

the on-chip amplifiers.

These devices also include a fourth order DS mod-

ulator followed by a digital filter

which provides

eight selectable output word rates of

1.88 Sps,

3.76 Sps, 7.51 Sps, 15 Sps, 30 Sps, 61.6 Sps,

84.5 Sps, and 101.1 Sps

(XIN = 32.768 kHz).

The

devices are capable of producing output update

rates up to 617 Sps when a 200 kHz clock is used

(CS5522/24/28) or up to 401 Sps using a 130 kHz

clock (CS5521/23). Further note that the digital fil-

ters are designed to settle to full accuracy within

one conversion cycle and simultaneously reject

both 50 Hz and 60 Hz interference when operated

at word rates below 30 Sps (assuming a XIN clock

frequency of 32.768 kHz).

To ease communication between the ADCs and a

micro-controller, the converters include an easy to

use three-wire serial interface which is SPI™ and

Microwire™ compatible.

1.1 Analog Input

Figure 4 illustrates a block diagram of the analog in-

put signal path inside the CS5521/22/23/24/28. The

front end consists of a multiplexer (break before

make configuration), a chopper-stabilized instru-

mentation amplifier with fixed gain of 20X,

coarse/fine charge buffers, and a programmable gain

section. For the 25 mV, 55 mV, and 100 mV input

ranges, the input signals are amplified by the 20X in-

strumentation amplifier. For the 1 V, 2.5 V, and 5 V

input ranges, the instrumentation amplifier is by-

passed and the input signals are connected to the

Programmable Gain block via coarse/fine charge

buffers.

VREF+

Differential

4th

order

delta-

sigma

modulator

Digital

Filter

Programmable

Gain

VREF-

NBV

X20

AIN2+

AIN2-

AIN1+

AIN1-

CS5522

IN+

IN-

AIN4+

AIN4-

AIN1+

AIN1-

CS5524

AIN8+

AIN7+

AIN1+

CS5528

IN+

IN-

IN+

IN-

IN+

IN-

Figure 4. Multiplexer Configurations

NBV also supplies the negative

supply voltage for the coarse/fine

change buffers

CS5521/22/23/24/28

14 DS317F8

1.1.1 Instrumentation Amplifier

The instrumentation amplifier is chopper stabilized

and is activated any time conversions are performed

with the low-level input ranges, ≤100 mV. The am-

plifier is powered from VA+ and from the NBV

(Negative Bias Voltage) pin allowing the

CS5521/22/23/24/28 to be operated in either of two

analog input configurations. The NBV pin can be bi-

ased to a negative voltage between -1.8 V and

-2.5 V, or tied to AGND (for the CS5528, NBV has

to be between -1.8 V and -2.5 V for the ranges below

100 mV when the amplifier is engaged). The com-

mon-mode-plus-signal range of the instrumentation

amplifier is 1.85 V to 2.65 V with NBV grounded.

The common-mode-plus-signal range of the instru-

mentation amplifier is -0.150 V to 0.950 V with

NBV between -1.8 V to -2.5 V. Whether NBV is

tied between -1.8 V and -2.5 V or tied to AGND,

the (Common Mode + Signal) input on AIN+ and

AIN- must stay between NBV and VA+.

Figure 5 illustrates an analog input model for the

ADCs when the instrumentation amplifier is en-

gaged. The CVF (sampling) input current for each

of the analog input pins depends on the CFS1 and

CFS0 (Chop Frequency Select) bits in the configu-

ration register (see Configuration Register for de-

tails). Note that the CVF current is lowest with the

CFS bits in their default states (cleared to logic 0s).

Further note that the CVF current into the instru-

mentation amplifier is less than 300 pA over -40°C

to +85°C. Note that Figure 5 is for input current

modeling only. For physical input capacitance see

‘Input Capacitance’ specification under ANALOG

CHARACTERISTICS. Also refer to Applications

Note AN30 - “Switched-Capacitor A/D Converter

Input Structures” for more details on input models

and input sampling currents.

Note: Residual noise appears in the converter’s baseband for

output word rates greater than 61.6 Sps if the CFS bits

are logic 0 (chop clock = 256 Hz). For word rates of

30 Sps and lower, 256 Sps chopping is recommended,

and for 61.6 Sps, 84.5 Sps and 101.1 Sps word rate set-

tings, 4096 Hz chopping is recommended.

1.1.2 Coarse/Fine Charge Buffers

The unity gain buffers are activated any time conver-

sions are performed with the high-level inputs rang-

es, 1 V, 2.5 V, and 5 V. The unity gain buffers are

designed to accommodate rail-to-rail input signals.

The common-mode-plus-signal range for the unity

gain buffer amplifier is NBV to VA+.

Typical CVF (sampling) current for the unity gain

buffer amplifiers is about 10 nA

(XIN = 32.768 kHz, see Figure 6).

AIN

25 mV, 55 mV, and 100 mV Ranges

C=48pF

CFS1/CFS0 = 00, f = 256 Hz

CFS1/CFS0 = 01, f = 4096 Hz

CFS1/CFS0 = 10, f = 16.384 kHz

CFS1/CFS0 = 11, f = 1024 Hz

≤

25 mV

i=fV C

osn

Figure 5. Input Models for AIN+ and AIN- pins, ≤100

mV Input Ranges

AIN

C=20pF

f=32.768kHz

Coarse

Fine

≤

25 mV

i=fV C

osn

1 V, 2.5 V and 5 V Ranges

Figure 6. Input Models for AIN+ and AIN- pins, >100

mV input ranges

CS5521/22/23/24/28

DS317F8 15

1.1.3 Analog Input Span Considerations

The CS5521/22/23/24/28 is designed to measure

full-scale ranges of 25 mV, 55 mV, 100 mV, 1 V,

2.5 V, and 5 V. Other full scale values can be ac-

commodated by performing a system calibration

within the limits specified. See the Calibration sec-

tion for more details. Another way to change the

full scale range is to increase or to decrease the

voltage reference to a voltage other than 2.5 . See

the Voltage Reference section for more details.

Three factors set the operating limits for the input

span. They include: instrumentation amplifier satu-

ration, modulator 1’s density, and a lower reference

voltage. When the 25 mV, 55 mV, or 100 mV

range is selected, the input signal (including the

common-mode voltage and the amplifier offset

voltage) must not cause the 20X amplifier to satu-

rate in either its input stage or output stage. To pre-

vent saturation, the absolute voltages on AIN+ and

AIN- must stay within the limits specified (refer to

the Analog Input section). Additionally, the differ-

ential output voltage of the amplifier must not ex-

ceed 2.8 V. The equation

ABS(VIN + VOS) x 20 = 2.8 V

defines the differential output limit, where

VIN = (AIN+) - (AIN-)

is the differential input voltage and VOS is the ab-

solute maximum offset voltage for the instrumenta-

tion amplifier (VOS will not exceed 40 mV). If the

differential output voltage from the amplifier ex-

ceeds 2.8 V, the amplifier may saturate, which will

cause a measurement error.

The input voltage into the modulator must not

cause the modulator to exceed a low of 20 percent

or a high of 80 percent 1's density. The nominal

full-scale input span of the modulator (from 30 per-

cent to 70 percent 1’s density) is determined by the

VREF voltage divided by the Gain Factor. See

Table 1 to determine if the CS5521/22/23/24/28 is

being used properly. For example, in the 55 mV

range, to determine the nominal input voltage to the

modulator, divide VREF (2.5 V) by the Gain Fac-

tor (2.2727).

When a smaller voltage reference is used, the re-

sulting code widths are smaller causing the con-

verter output codes to exhibit more changing codes

for a fixed amount of noise. Table 1 is based upon

a VREF = 2.5 V. For other values of VREF, the

values in Table 1 must be scaled accordingly.

1.1.4 Measuring Voltages Higher than 5 V

Some systems require the measurement of voltages

greater than 5 V. The input current of the instru-

Note: 1. The converter's actual input range, the delta-sigma's nominal full-scale input, and the delta-sigma's

maximum full-scale input all scale directly with the value of the voltage reference. The values in the

table assume a 2.5

V VREF voltage.

2. The 2.8 V limit at the output of the 20X amplifier is the differential output voltage.

Input Range

(1)

Max. Differential Output

20X Amplifier

VREF Gain Factor

Δ-Σ Nominal

(1)

Differential Input

Δ-Σ

(1)

Max. Input

± 25 mV

2.8 V

(2)

2.5V 5 ± 0.5 V ± 0.75 V

± 55 mV

2.8 V

(2)

2.5V 2.272727... ± 1.1 V ± 1.65 V

± 100 mV

2.8 V

(2)

2.5V 1.25 ± 2.0 V ± 3.0 V

± 1.0 V - 2.5V 2.5 ± 1.0 V ± 1.5 V

± 2.5 V - 2.5V 1.0 ± 2.5 V ± 5.0 V

± 5.0 V - 2.5V 0.5 ± 5.0 V 0V, VA+

Table 1. Relationship between Full Scale Input, Gain Factors, and Internal Analog

Signal Limitations

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P56

CS5521-ASZ

Mfr. #:

Buy CS5521-ASZ

Manufacturer:

Cirrus Logic

Description:

Analog to Digital Converters - ADC 2-Ch 16-Bit Delta Sigma ADC

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CS5521-ASZ

CS5521-ASZ

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