CS5521/22/23/24/28
40 DS317F8
of the configuration register.
4) Once the CSRs are programmed, repeated conver-
sions on up to 16 Setups can be performed by is-
suing only one command byte.
5) The single conversion mode also requires only one
command, but whenever another or a different
single conversion is wanted, this command or a
modified version of it has to be issued again.
6) The NULL command is used to keep the serial port
in command mode, once it is in command mode.
1.5 Conversion Output Coding
The CS5521/22/23/24/28 devices output 16-bit
(CS5521/23) and 24-bit (CS5522/24/28) data con-
version words. To read a conversion word, the user
must read the conversion data FIFO. The conver-
sion data FIFO is up to 192 bits long and outputs
the conversions MSB first. The last byte of the con-
version data word (CS5521/23 only) contains data
monitoring flags. The channel indicator (CI) bits
keep track of which physical channel was convert-
ed, and the overrange flag (OF) and the oscillation
detect (OD) bits monitor conversions to determine
if a valid conversion was performed. Refer to the
Conversion Data FIFO Descriptions section for
more details.
The CS5521/22/23/24/28 output data conversions
in binary format when operating in unipolar mode
and in two's complement when operating in bipolar
mode. Refer to the Conversion Data FIFO De-
scriptions section for more details.
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the
voltage between ± full scale for any of the bipolar gain ranges. See text about error flags under overrange
conditions.
Unipolar Input
Voltage
Offset
Binary
Bipolar Input
Voltage
Two's
Complement
Unipolar Input
Voltage
Offset
Binary
Bipolar Input
Voltage
Two's
Complement
>(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB) 7FFF >(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB) 7FFFFF
VFS-1.5 LSB FFFF
------
FFFE
VFS-1.5 LSB
7FFF
------
7FFE
VFS-1.5 LSB FFFFFF
------
FFFFFE
VFS-1.5 LSB
7FFFFF
------
7FFFFE
VFS/2-0.5 LSB 8000
------
7FFF
-0.5 LSB
0000
------
FFFF
VFS/2-0.5 LSB 800000
------
7FFFFF
-0.5 LSB
000000
------
FFFFFF
+0.5 LSB 0001
------
0000
-VFS+0.5 LSB
8001
------
8000
+0.5 LSB 000001
------
000000
-VFS+0.5 LSB
800001
------
800000
<(+0.5 LSB) 0000 <(-VFS+0.5 LSB) 8000 <(+0.5 LSB) 000000 <(-VFS+0.5 LSB) 800000
Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28
CS5521/23 16-Bit Output Coding CS5522/24/28 24-Bit Output Coding
CS5521/22/23/24/28
DS317F8 41
1.5.1 Conversion Data FIFO Descriptions
CS5521/23 (EACH 16-BIT CONVERSIONS)
CS5522/24/28 (EACH 24-BIT CONVERSION LEVELS)
Conversion Data Bits [23:8 for CS5521/23; 23:0 for CS5522/24/28]
These bits depict the latest output conversion.
OD (Oscillation detect Flag Bit)
0 Bit is clear when oscillatory condition in modulator does not exist (bit is read only).
1 Bit is set any time an oscillatory condition is detected in the modulator. This does not occur under normal
operation conditions, but may occur when the input is extremely overranged. The OD flag will be cleared
to logic 0 when the modulator becomes stable.
OF (Over-range Flag Bit)
0 Bit is clear when over-range condition has not occurred (bit is read only).
1 Bit is set when input signal is more positive than the positive full scale, more negative than zero (unipolar
mode) or when the input is more negative than the negative full scale (bipolar mode).
CI (Channel Indicator Bits) [1:0]
These bits indicate which physical input channel was converted.
00 Physical Channel 1 (CS5521/23 only)
01 Physical Channel 2 (CS5521/23 only)
10 Physical Channel 3 (CS5523 only)
11 Physical Channel 4 (CS5523 only)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
MSB1413121110987654
D11 D10D9D8D7D6 D5D4D3D2D1D0
3 2 1 LSB 1 1 1 0 CI1 CI0 OD OF
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
MSB 2221201918 171615141312
D11 D10D9D8D7D6 D5D4D3D2D1D0
11 10 9 8 7 6 5 4 3 2 1 LSB
CS5521/22/23/24/28
42 DS317F8
1.6 Digital Filter
The CS5521/22/23/24/28 have eight different lin-
ear phase digital filters which set the output word
rates (OWRs) shown in Table 3. These rates as-
sume that XIN is 32.768 kHz. Each of the filters
has a magnitude response similar to that shown in
Figure 18. The filters are optimized to settle to full
accuracy every conversion and yield better than
80 dB rejection for both 50 and 60 Hz with output
word rates at or below 15.0 Sps.
The converter’s digital filters scale with XIN. For
example with an output word rate of 15 Sps, the fil-
ter’s corner frequency is typically 12.7 Hz using a
32.768 kHz clock. If XIN is increased to
65.536 kHz the OWR doubles and the filter’s cor-
ner frequency moves to 25.4 Hz.
1.7 Clock Generator
The CS5521/22/23/24/28 include a gate which can
be connected with an external crystal to provide the
master clock for the chip. The chips are designed to
operate using a low-cost 32.768 kHz “tuning fork”
type crystal. One lead of the crystal should be con-
nected to XIN and the other to XOUT. Lead lengths
should be minimized to reduce stray capacitance.
Note that the oscillator circuit will also operate
with a 100 kHz “tuning fork” type crystal.
The converters will operate with an external
(CMOS compatible) clock with frequencies up to
130 kHz (CS5521/23) or 200 kHz (CS5522/24/28).
Figures 19 and 20 detail the CS5521/23 and
CS5522/24/28’s performance (respectively) at in-
creased clock rates.
The 32.768 kHz crystal is normally specified as a
time-keeping crystal with tight specifications for
both initial frequency and for drift over tempera-
ture. To maintain excellent frequency stability,
these crystals are specified only over limited oper-
ating temperature ranges (i.e. -10° C to +60° C).
However, applications with the
CS5521/22/23/24/28 don’t generally require such
tight tolerances.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
Attenuation (dB)
1234
5
6
7
8 9 10 11 12 13 14 15
for OWR = 15.0 Sps
f1 = 47.5 Hz
f2 = 65.5 Hz
fS/2 = XIN/4
f1
f2
15 Sps
0.0004
0.0006
0.0008
0.001
0.0012
0.0014
0.0016
0.0018
0.002
30 50 70 90 110 130
XIN (kHz)
Linearity Error (%FS)
Figure 19. Typical Linearity Error for CS5521/23
0.0004
0.0005
0.0006
0.0007
0.0008
0.0009
0.001
0.0011
0.0012
0.0013
20 40 60 80 100 120 140 160 180 200
XIN (kHz)
Linearity Error (%FS)
Figure 20. Typical Linearity Error for CS5522/24/28

CS5521-ASZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Analog to Digital Converters - ADC 2-Ch 16-Bit Delta Sigma ADC
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