723622L15PFG Datasheet 723622L15PFG, 723642L15PFG, 723632L15PFG | P10-P12

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

timing diagrams for port B can be found in Figure 5 and 6.

The setup and hold time constraints to the port Clocks for the port Chip

Selects and Write/Read selects are only for enabling write and read

operations and are not related to high-impedance control of the data

outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select

and Write/Read select may change states during the setup and hold time

window of the cycle.

When a FIFO Output Ready flag is LOW, the next word written is

automatically sent to the FIFO output register automatically by the LOW-to-HIGH

transition of the port clock that sets the Output Ready flag HIGH. When the Output

Ready flag is HIGH, subsequent data is clocked to the output registers only when

a FIFO read is selected using the port’s Chip Select, Write/Read select, Enable,

and Mailbox select.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through at least two flip-flop

stages. This is done to improve flag-signal reliability by reducing the

probability of metastable events when CLKA and CLKB operate asynchro-

nously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA.

ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show

the relationship of each port flag to FIFO1 and FIFO2.

OUTPUT READY FLAGS (ORA, ORB)

The Output Ready flag of a FIFO is synchronized to the port clock that

reads data from its array. When the Output Ready flag is HIGH, new data

is present in the FIFO output register. When the Output Ready flag is LOW,

the previous data word is present in the FIFO output register and attempted FIFO

reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to

its output register. The state machine that controls an Output Ready flag monitors

a write pointer and read pointer comparator that indicates when the FIFO

memory status is empty, empty+1, or empty+2. From the time a word is written

to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles

of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag

is LOW if a word in memory is the next data to be sent to the FlFO output register

and three cycles of the port Clock that reads data from the FIFO have not elapsed

since the time the word was written. The Output Ready flag of the FIFO remains

LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs,

simultaneously forcing the Output Ready flag HIGH and shifting the word to the

FIFO output register.

A LOW-to-HIGH transition on an Output Ready flag synchronizing clock

begins the first synchronization cycle of a write if the clock transition occurs at

time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can

be the first synchronization cycle (see Figures 8 and 9 for ORA and ORB timing

diagrams).

INPUT READY FLAGS (IRA, IRB)

The Input Ready flag of a FlFO is synchronized to the port clock that writes

data to its array. When the Input Ready flag is HIGH, a memory location is free

in the FIFO to receive new data. No memory locations are free when the Input

Ready flag is LOW and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. The

state machine that controls an Input Ready flag monitors a write pointer and read

CSB W/RB ENB MBB CLKB Data B (B0-B35) I/O PORT FUNCTION

H X X X X High-Impedance None

L L L X X Input None

LLHL↑ Input FIFO2 write

LLHH↑ Input Mail2 write

L H L L X Output None

LHHL↑ Output FIFO1 read

L H L H X Output None

LHHH↑ Output Mail1 read (set MBF1 HIGH)

TABLE 3 — PORT B ENABLE FUNCTION TABLE

TABLE 2 — PORT A ENABLE FUNCTION TABLE

CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O PORT FUNCTION

H X X X X High-Impedance None

L H L X X Input None

LHHL↑ Input FIFO1 write

LHHH↑ Input Mail1 write

L L L L X Output None

LLHL↑ Output FIFO2 read

L L L H X Output None

LLHH↑ Output Mail2 read (set MBF2 HIGH)

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

a write pointer and read pointer comparator that indicates when the FIFO

memory status is almost-empty, almost-empty+1, or almost-empty+2. The

almost-empty state is defined by the contents of register X1 for AEB and

a FIFO reset or programmed from port A (see Almost-Empty flag and

Almost-Full flag offset programming section). An Almost-Empty flag is

LOW when its FIFO contains X or less words and is HIGH when its FIFO

contains (X+1) or more words. A data word present in the FIFO output

Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing

clock are required after a FIFO write for its Almost-Empty flag to reflect the new

level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more

words remains LOW if two cycles of its synchronizing clock have not elapsed

since the write that filled the memory to the (X+1) level. An Almost-Empty flag

is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after

the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of

an Almost-Empty flag synchronizing clock begins the first synchronization cycle

if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.

Synchronized Synchronized

Number of Words in FIFO

(1,2)

to CLKB to CLKA

IDT723622

(3)

IDT723632

(3)

IDT723642

(3)

ORB AEB A FA IRA

000LLHH

1 to X1 1 to X1 1 to X1 H L H H

(X1+1) to [256-(Y1+1)] (X1+1) to [512-(Y1+1)] (X1+1) to [1,024-(Y1+1)] H H H H

(256-Y1) to 255 (512-Y1) to 511 (1,024-Y1) to 1,023 H H L H

256 512 1,024 H H L L

pointer comparator that indicates when the FlFO memory status is full,

full-1, or full-2. From the time a word is read from a FIFO, its previous

memory location is ready to be written in a minimum of two cycles of the

Input Ready flag synchronizing clock. Therefore, an Input Ready flag is

LOW if less than two cycles of the Input Ready flag synchronizing clock

have elapsed since the next memory write location has been read. The

second LOW-to-HIGH transition on the Input Ready flag synchronizing

Clock after the read sets the Input Ready flag HIGH.

A LOW-to-HIGH transition on an Input Ready flag synchronizing

clock begins the first synchronization cycle of a read if the clock transition

occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent

clock cycle can be the first synchronization cycle (see Figures 10 and 11

for timing diagrams).

ALMOST-EMPTY FLAGS (AEA, AEB)

The Almost-Empty flag of a FIFO is synchronized to the port clock that reads

data from its array. The state machine that controls an Almost-Empty flag monitors

NOTES:

1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read

operation necessary), it is not included in the FIFO memory count.

3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or

programmed from port A.

Synchronized Synchronized

Number of Words in FIFO

(1,2)

to CLKA to CLKB

IDT723622

(3)

IDT723632

(3)

IDT723642

(3)

ORA AEA A FB IRB

000LLHH

1 to X2 1 to X2 1 to X2 H L H H

(X2+1) to [256-(Y2+1)] (X2+1) to [512-(Y2+1)] (X2+1) to [1,024-(Y2+1)] H H H H

(256-Y2) to 255 (512-Y2) to 511 (1,024-Y2) to 1,023 H H L H

256 512 1,024 H H L L

NOTES:

1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.

2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read

operation necessary), it is not included in the FIFO memory count.

3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or

programmed from port A.

TABLE 4 — FIFO1 FLAG OPERATION

TABLE 5 — FIFO2 FLAG OPERATION

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-

to-HIGH transition of its synchronizing clock after the FIFO read that

reduces the number of words in memory to [256/512/1,024-(Y+1)]. A

LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins

the first synchronization cycle if it occurs at time tSKEW2 or greater after the

read that reduces the number of words in memory to [256/512/1,024-

(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the

first synchronization cycle (see Figures 14 and 15).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

information between port A and port B without putting it in queue. The

Mailbox select (MBA, MBB) inputs choose between a mail register and a

FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA

writes A0-A35 data to the mail1 register when a port A Write is selected by CSA,

W/RA, and ENA and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes

B0-B35 data to the mail2 register when a port B Write is selected by CSB, W/

RB, and ENB and with MBB HIGH. Writing data to a mail register sets its

corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register

are ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus comes from

the FIFO output register when the port Mailbox select input is LOW and from

the mail register when the port-mailbox select input is HIGH. The Mail1

a port B Read is selected by CSB, W/RB, and ENB and with MBB HIGH. The

Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA

when a port A read is selected by CSA, W/RA, and ENA and with MBA HIGH.

The data in a mail register remains intact after it is read and changes only when

new data is written to the register. For mail register and Mail Register flag timing

diagrams, see Figure 16 and 17.

Otherwise, the subsequent synchronizing clock cycle may be the first

synchronization cycle. (See Figures 12 and 13).

ALMOST-FULL FLAGS (AFA, AFB)

The Almost-Full flag of a FIFO is synchronized to the port clock that

writes data to its array. The state machine that controls an Almost-Full flag

monitors a write pointer and read pointer comparator that indicates when

the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The

almost-full state is defined by the contents of register Y1 for AFA and

a FlFO reset or programmed from port A (see Almost-Empty flag and

Almost-Full flag offset programming section). An Almost-Full flag is

LOW when the number of words in its FIFO is greater than or equal to

(256-Y), (512-Y), or (1,024-Y) for the IDT723622, IDT723632, or

IDT723642 respectively. An Almost-Full flag is HIGH when the number

of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or

[1,024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respec-

tively. Note that a data word present in the FIFO output register has been

read from memory.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock

are required after a FIFO read for its Almost-Full flag to reflect the new level of

fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)]

or less words remains LOW if two cycles of its synchronizing clock have not

elapsed since the read that reduced the number of words in memory to [256/

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

723622L15PFG

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Description:

FIFO 256 x 36 x 2 Sync BiFIFO 5.0V 8ns

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723622L15PFG

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