1.tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty
CSA
WRA
MBA
IRA
A0 - A35
CLKB
ORB
ENA
CLKA
12
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
POR
FIFO1 Empty
LOW
HIGH
t
CLKH
W1
HIGH
(1)
t
POR
t
A
t
ENS2
t
ENH
W1
4660 drw 10
Old Data in FIFO1 Output Register
LOW
CSB
HIGH
LOW
MBB
W/RB
ENB
B0 - B35
17
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 9. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
CSB
W/RB
MBB
IRB
B0 - B35
CLKA
ORA
CSA
W/RA
MBA
ENB
ENA
A0-A35
CLKB
3022 drw 11
12
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKH
t
POR
t
POR
t
ENS2
t
ENH
t
A
Old Data in FIFO2 Output RegisterW1
FIFO2 Empty
t
CLKL
LOW
LOW
LOW
LOW
LOW
HIGH
W1
(1)
18
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1.tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 10. IRA Flag Timing and First Available Write when FIFO1 is Full
