4
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Symbol Name I/O Description
ORA Output Ready O ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is LOW, FIFO2 is
Flag (Port A) empty and reads from its memory are disabled. Ready data is present on the output register
of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the
third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory.
ORB Output Ready O ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB is LOW, FlFO1 is
Flag (Port B) empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1
when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-to-
HIGH transition of CLKB after a word is loaded to empty memory.
RST1 FIFO1 Reset I To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0
and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is
written to its RAM.
RST2 FIFO2 Reset I To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0
and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is
written to its RAM.
W/RA Port A Write/ I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Read Select transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
W/RB Port B Write/ I A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
Read Select transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.
PIN DESCRIPTIONS (CONTINUED)
5
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Characterized values, not currently tested.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT723622
IDT723632
IDT723642
Commercial
t
CLK = 15 ns
Symbol Parameter Test Conditions Min. Typ.
(1)
Max. Unit
V
OH Output Logic "1" Voltage VCC = 4.5V, IOH = –4 mA 2.4 V
V
OL Output Logic "0" Voltage VCC = 4.5V, IOL = 8 mA 0.5 V
ILI Input Leakage Current (Any Input) VCC = 5.5V, VI = VCC or 0 ±10 μA
I
LO Output Leakage Current VCC = 5.5V, VO = VCC or 0 ±10 μA
I
CC2
(2)
Standby Current (with CLKA & CLKB running) VCC = 5.5V, VI = VCC –0.2V or 0V 8 mA
ICC3
(2)
Standby Current (no clocks running) VCC = 5.5V, VI = VCC –0.2V or 0V 1 mA
C
IN
(3)
Input Capacitance VI = 0, f = 1 MHz 4 pF
C
OUT
(3)
Output Capacitance VO = 0, f = 1 MHZ 8 pF
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
V
CC Supply Voltage (Commercial) 4.5 5.0 5.5 V
VIH High-Level Input Voltage (Commercial) 2 V
V
IL Low-Level Input Voltage (Commercial) 0.8 V
I
OH High-Level Output Current (Commercial) 4 mA
IOL Low-Level Output Current (Commercial) 8 mA
T
A Operating Temperature (Commercial) 0 70 °C
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(1)
Symbol Rating Commercial Unit
V
CC Supply Voltage Range –0.5 to 7 V
V
I
(2)
Input Voltage Range –0.5 to VCC+0.5 V
VO
(2)
Output Voltage Range –0.5 to VCC+0.5 V
I
IK Input Clamp Current (VI < 0 or VI > VCC) ±20 mA
I
OK Output Clamp Current (VO = < 0 or VO > VCC) ±50 mA
I
OUT Continuous Output Current (VO = 0 to VCC) ±50 mA
I
CC Continuous Current Through VCC or GND ±400 mA
T
STG Storage Temperature Range –65 to 150 ° C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
6
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA
and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x ΔICC x dc)] + Σ(CL x VCC
2
X fo)
where:
N = number of outputs = 36
ΔICC = increase in power supply current for each input at a TTL HIGH level
dc = duty cycle of inputs at a TTL HIGH level of 3.4 V
CL = output capacitance load
fo = switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS)
010 20 30 40 50 60 70
0
50
100
250
300
V
CC
= 5.0V
f
S
Clock Frequency MHz
f
data
= 1/2 f
S
T
A
= 25°C
C
L
= 0pF
V
CC
= 5.5V
3022 drw 03a
200
150
V
CC
= 4.5V
80 90
I
CC(f)
Supply Current mA

723622L15PFG

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 256 x 36 x 2 Sync BiFIFO 5.0V 8ns
Lifecycle:
New from this manufacturer.
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