13
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
NOTE:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight
(1)
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and
rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
3022 drw 05
CLKA
RST1,
RST2
IRA
CLKB
IRB
A0 - A35
FS1,FS0
ENA
t
FSS
t
FSH
t
PIR
t
ENH
t
ENS2
t
SKEW1
t
DS
t
DH
t
PIR
4
0,0
AFA Offset
(Y1)
AEB Offset
(X1)
AFB Offset
(Y2)
AEA Offset
(X2)
First Word to FIFO1
1
2
(1)
12
CLKA
RST1
IRA
AEB
AFA
MBF1
CLKB
ORB
FS1,FS0
3022 drw 04
t
RSTS
t
RSTH
t
FSH
t
FSS
t
PIR
t
PIR
t
POR
t
RSF
0,1
t
RSF
t
RSF
