DATASHEET
VERSACLOCK
®
LOW POWER CLOCK GENERATOR IDT5P49EE502
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 1
IDT5P49EE502 REV L 111714
Description
The IDT5P49EE502 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to five differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal.
The IDT5P49EE502 can be programmed through the use
of the I
2
C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise. It also may operate in standard spread
spectrum mode.
There are total five 8-bit output dividers. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
Target Applications
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
Features
Four internal PLLs
Internal non-volatile EEPROM
Internal I
2
C EEPROM master interface
FAST (400kHz) mode I
2
C serial interfaces
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
Output Frequency Ranges: kHz to 120 MHz
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
8-bit output-divider blocks
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
2 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10A max in power down mode
1.8V VDD Core Voltage
Available in 20pin 3x3mm QFN packages
-40 to +85 C Industrial Temp operation
IDT5P49EE502
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 2
IDT5P49EE502 REV L 111714
Functional Block Diagram
PLLA
PLLB(SS)
PLLC
PLLD
/DIV3
/DIV2
/DIV4
XIN/REF
XOUT
SDA
SCL
SEL
OUT2
OUT3
OUT4
S
R
C
1
S
R
C
2
S
R
C
3
S
R
C
4
Control
Logic
GND
VDD VDDO2VDDO1
/DIV1
OUT1
/DIV0
OUT0
S
R
C
0
IDT5P49EE502
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 3
IDT5P49EE502 REV L 111714
Pin Assignment
Pin Descriptions
Pin Name Pin # I/O Pin Type Pin Description
XOUT 1 O LVTTL MHz CRYSTAL_OUT -- Reference crystal feedback. Float pin if
using reference input clock.
XIN/ REF 2 I LVTTL MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input. Maximum clock input voltage is 1.8V.
GND 3 Power Connect to Ground.
OUT3 4 O OUTPUT Buffered reference clock output. Single-ended output voltage
levels are register controlled by either VDDO1 or VDDO2.
SEL0* 5 I LVTTL Configuration select pin. Weak internal pull down resistor.
VDD 6 Power Device power supply. Connect to 1.8V.
VDDx 7 Power Device power supply. Connect to 1.8V.
VDDO1 8 Power Device power supply. Connect to 1.8 to 3.3V. VDDO1 must be
the highest voltage on the device. Using register settings, select
output voltage levels for OUT0-OUT3.
GND 9 Power Connect to Ground.
OUT2 10 O Adjustable Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
OUT1 11 O Adjustable Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
SEL1* 12 I LVTTL Configuration select pin. Weak internal pull down resistor.
GND 13 Power Connect to Ground.
1
XOUT
20- pin QFN
XIN/REF
GND
OUT0
SCLK
GND
SEL1
VDDO1
6
11
16
OUT3
OUT1
OUT2
GND
VDD
VDDx
VDDO2
SDA
VDD
GND
OUT4
SEL0

5P49EE502NDGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products VERSACLOCK LOW POWER PLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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