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5P49EE502NDGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
IDT5P49EE502
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 4
IDT5P49EE502 REV L 111714
Note *: SEL pins should be controlled by 1.8V LVTTL logic; 3.3V tolerant.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL as indicated above. Always
completely power up VDD and VDDx prior to applying VDDO power.
Note 2: Default configuration CLK3=Buffered Reference output. All other outputs are off.
Note 3: Do not power up with SEL[1:0] = 00 (in Power down/Sleep mode).
Ideal Power Up Sequence Ideal Power Down Sequence
SCLK 14 I LVTTL I
2
C clock. Logic levels set by VDDO1. 5V tolerant.
OUT0 15 O Adjustable Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1 or VDDO2.
OUT4 16 O Adjustable Configurable clock output 8. Single-ended output voltage levels
controlled by VDDO2.
SDA 17 I/O Open Drain Bidirectional I
2
C data. Logic levels set by VDDO1. 5V tolerant.
VDDO2 18 Power Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT4.
VDD 19 Power Device power supply. Connect to 1.8V.
GND 20 Power Connect to Ground.
V
t
V
DD
, V
DD
x
V
DD
O1
V
DD
O2, V
DD
O3
1) V
DD
and V
DD
x must come up first, followed by V
DD
O
2) V
DD
O1 must come up within 1ms after VDD and VDDX come up
3) V
DD
O2 must be equal to, or lower than, V
DD
O1
4) V
DD
and V
DD
x have approx. the same ramp rate
5) V
DD
O1 and V
DD
O2 have approx. same ramp rate
1 ms
V
t
V
DD
, V
DD
x
V
DD
O1
1) V
DD
O must drop first, followed by V
DD
and V
DD
x
2) V
DD
and V
DD
x must come down within 1ms after V
DD
O1 comes down
3) V
DD
O2 must be equal to, or lower than, V
DD
O1
4) V
DD
and V
DD
x have approx. the same ramp rate
5) V
DD
O1 and V
DD
O2 have approx. same ramp rate
V
DD
O2, V
DD
O3
1 ms
IDT5P49EE502
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 5
IDT5P49EE502 REV L 111714
PLL Features and Descriptions
PLL Block Diagram
Crystal Input (XIN/REF)
The crystal oscillators should be fundamental mode quartz
crystals; overtone crystals are not suitable. Crystal
frequency should be specified for parallel resonance with
50 maximum equivalent series resonance. 0
ONXTALB=0 bit needs to be set for XIN/REF.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The crystal cpacitors are internal to the device and have an
effective value of 4pF.
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
Where F
IN
is the reference frequency, XDIV is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and F
OUT
is the resulting output frequency. Programming
any of the dividers may cause glitches on the outputs.
Ref-Divider
(D) Values
Feedback
Pre-Divider
(XDIV)
Values
Feedback
(M) Values
Programmable
Loop Bandwidth
Spread Spectrum
Generation Capability
PLLA 1 - 255 1 or 4 6 - 2047 Yes No
PLLB 1 - 255 4 6 - 2047 Yes Yes
PLLC 1 - 255 1 or 8 bit divide 6 - 2047 Yes No
PLLD 1 - 255 1 or 4 6 - 2047 Yes No
VCO
D
XDIVM
( )
F
OUT
=
XDIV*M
D
F
IN
*
ODIV
(Eq. 2)
IDT5P49EE502
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 6
IDT5P49EE502 REV L 111714
SPREAD SPECTRUM GENERATION
(PLLB)
PLLB has spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The programmable spread
spectrum generation parameters are NC[10:0], MOD[12:0],
and NSS[10:0] bits. To enable spread spectrum, set
SSENB_B=0.
The spread spectrum circuitry was specifically developed to
accommodate video display applications. The spread
modulation frequency can be defined to exactly equal the
horizontal line frequency (HSYNC)
NC[10:0]
These bits are used to determine the number of pulses per
spread spectrum cycle. For video applications, NC is the
number of pixels on the horizontal display row (or integer
multiple of displayed pixels in a row). By matching the
spread period to the screen, no tearing or “shimmer” will be
apparent.
NC must be an even number to insure that the upward
spread transition has the same number of steps as the
downward spread transition.
For non-video applications, this can also be seen as the
number of clock cycles for a complete spread spectrum
period.
MOD[12:0]
These bits relate the VCO frequency to the target average
spread output frequency (F
MID
).
F
MID
= (F
VCO
) / 8
F
MAX
= F
MID
+ (SS% * F
MID)
F
MIN
= F
MID
- (SS% * F
MID)
MOD = (F
REF
* NC) / (2 * F
MID
)
NSS[10:0]
These bits control the amplitude of the spread modulation.
NSS = (NC / 2) + (NC / 8) * (F
MAX
- F
MIN
) / F
MID
Modulation frequency:
F
MOD
= F
MID
/ NC (Eq. 11)
Video Example
F
REF
= 27 MHz, F
OUT
= 27 MHz, 640 pixels per line, center
spread of ±1%. Using F
VCO
=432MHz, find the necessary
spread spectrum register settings.
F
MID
= F
VCO
/8
NC = 640 (integer number of spread periods/screen)
MOD = (25MHz * 640)/(2 * 54MHz) = 160
NSS = (640/2)+(640/8)*(27.27MHz-26.73MHz)/27MHz =
321.
F
MOD
= 27MHz/640 = 11.8kHz.
Non-Video Example
F
REF
= 25MHz, F
OUT
= 27 MHz, 31.25kHz modulation rate,
center spread of ±1%. Find the necessary spread spectrum
register settings.
F
MID
= F
VCO
/ 8
F
MOD
= 31.25kHz = 50.625MHz/NC.
NC = 1620
MOD = (25MHz * 1620)/(2 * 50.625MHz) = 400
NSS = (1620/2)+(1620/8)*(27.27MHz-26.73MHz)/27MHz =
814.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

5P49EE502NDGI

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Buy 5P49EE502NDGI
Manufacturer:
IDT
Description:
Clock Generators & Support Products VERSACLOCK LOW POWER PLL
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