IDT5P49EE502
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 25
IDT5P49EE502 REV L 111714
Revision History
Rev. Date Originator Description of Change
-- 10/27/09 R.Willner Initial Preliminary Datasheet
A 11/10/09 R.Willner Revised pinout.
B 3/25/10 R.Willner Typographical changes. Register corrections. Correct spread spectrum calculations.
C 6/11/10 R. Willner Default configuration. Clarification of OUT4 is tied to VDDO2.
D 07/26/10 R. Willner Updated thermal pad and dimensions on package drawing.
E 8/30/10 R.Willner Input Clock max voltage swing 1.8V.
F 9/08/10 R.Willner Power ramp sequence.
G 10/18/10 R.Willner Typographical changes. Loop filter calculations. Default register bit corrections.
H 01/19/11 R.Willner Corrected notes for top-side marking.
J 04/13/11 R. Willner 1. Updated SCLK and SDA pin descriptions
2. Updated DC Electrical Char table for 1.8V LVTTL; added VIH and VIL.
3. Updated “Lock Time/PLL Lock Time from shutdown mode” Typ. and Max. specs in AC
Timing Electrical Char table.
K 09/30/11 R. Willner Updated Power-up/Power-down Sequence notes.
L 11/17/14 R. Willner Aded pin 1 dot indicator on marking diagram.
Corrected typo in Register Map table; SLEWx[0:1] was changed to SLEWx[1:0]
