IDT5P49EE502
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 8
IDT5P49EE502 REV L 111714
PLL Loop Bandwidth:
Charge pump gain (K) = Ip / 2
VCO gain (K
VCO) = 350MHz/V * 2
M = Total multiplier value (See the PRE-SCALERS,
FEEDBACK-DIVIDERS, POST-DIVIDERS section for more
detail)
c = (Rz * K* K
VCO * Cz)/(M * (Cz + Cp))
Fc = c / 2
Note, the phase/frequency detector frequency (F
PFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce your phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (m)
would need to be calculated as follows.
Phase Margin:
z = 1 / (Rz * Cz)
p = (Cz + Cp)/(Rz * Cz * Cp)
m = (360 / 2) * [tan
-1
(c/ z) - tan
-1
(c/ p)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
Damping Factor:
= Rz/2 *(KVCO * Ip * Cz)
1/2
/M
Example
Fc = 150KHz is the desired loop bandwidth. The total A*M
value is 160. The (damping factor) target should be 0.7,
meaning the loop is critically damped. Given Fc and A*M, an
optimal loop filter setting needs to be solved for that will
meet both the PLL loop bandwidth and maintain loop
stability.
Choose a mid-range charge pump from register table
Icp= 11.9uA.
K* K
VCO = 350MHz/V * 40uA = 12000A/Vs
c = 2* Fc = 9.42x10
5
s
-1
p = (Cz + Cp)/(Rz * Cz * Cp) = z (1 + Cz / Cp)
Solving for Rz, the best possible value Rz=30kOhms
(RZ[1:0]=10) gives
= 1.4 (Ideal range for is 0.7 to 1.4)
Solving back for the PLL loop bandwidth, Fc=149kHz.
The phase margin must be checked for loop stability.
m = (360 / 2) * [tan
-1 (9.42x10
5
s
-1
/ 1.19x10
5
s
-1
)
- tan
-1
(9.42x10
5
s
-1
/ 1.23x10
6
s
-1
)] = 45°
The phase margin would be acceptable with a fairly stable
loop.
