NXP Semiconductors
SL3S4011_4021
UCODE I²C
SL3S4011_4021 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 3.5 — 18 September 2018
COMPANY PUBLIC 204935 18 / 30
11.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending 8 bits
of data. During the ninth clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
11.5 Data input
During data input, the UCODE I
2
C samples Serial Data (SDA) on the rising edge of Serial
Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the
rising edge of Serial Clock (SCL). The Serial Data (SDA) signal must change only when
Serial Clock (SCL) is driven low.
11.6 Addressing
To start communication between a bus master and the UCODE I
2
C slave device, the
bus master must initiate a Start condition. Following this, the bus master sends the
device select code. The 7-bit device select code consists of a 4-bit device identifier (value
Ah) which is initialized in wafer test and cannot be changed in the user mode. Three
additional bits in the configuration word are reserved to alter the device address via RF
interface after initialization. This allows up to eight UCODE I
2
C devices to be connected
to a bus master at the same time.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write
operations.
If a match occurs on the device select code, the UCODE I
2
C gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the UCODE I
2
C does not match the device
select code, it deselects itself from the bus.
Table 15. Device select code
Device type identifier Device address in
configuration word 204h
to 206h
R/W
Device select
code
b7 b6 b5 b4 b3 b2 b1 b0
Value 1 0 1 0 0
[1]
0
[1]
1
[1]
1/0
[1] Initial values - can be changed - See also Table 9 and Table 10.
Table 16. I
2
C addressing
Most significant
byte
b15 b14 b13 b12 b11 b10 b9 b8
EPC address EPC/Lock EPC memory
bank
EPC memory word address
Least
significant byte
b7 b6 b5 b4 b3 b2 b1 b0
EPC address EPC memory word address MSB/
LSB
