MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
6 _______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
9 SLBO-
Negative System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock
as shown in Table 1.
10 SLBO+
Positive System Loop-Back Output or 622MHz/666MHz Clock Output. Select CML data or clock as
shown in Table 1.
12 SLBPD
System Loopback Power Down, TTL Input. SLPD = high activates the system loopback output
driver; SLBPD = low powers down the loop-back output driver.
13 SLBEN
System Loop-Back Enable Input, TTL Input. SLBEN = high activates the system loop-back output;
SLBEN = low
activates the 622MHz/666MHz reference clock output.
14 RESET
FIFO Reset, TTL Input. An active-high reset recenters the FIFO to tolerate maximum skew between
PCLKI and PCLKO.
15 FIFOERROR
FIFO Error Indicator, TTL Output. Active high when the read/write clocks access the same FIFO
address. This signal may be used to control RESET.
17, 28, 36, 43 V
CC
Supply Voltage, +3.3V
18 LOL
Loss of Lock, TTL Output. An active low indicates that the VCO and reference frequency differ by
500ppm.
19 MODE
Clock Control Input:
MODE = GND; f
PCLKI
= 311.04MHz/333MHz with SCLKO active
MODE = 30kΩ to GND; f
PCLKI
= 311.04MHz/333MHz with SCLKO off
MODE = OPEN (float); f
PCLKI
= 622.08MHz/666MHz with SCLKO off
MODE = V
CC
; f
PCLKI
= 622.08MHz/666MHz with SCLKO active
20 PCLKI+
Positive Parallel Clock, LVDS Input. Data is written to the input register on the clock rising edge in
622Mbps mode and on both rising and falling edges in 311Mbps mode (Figure 1).
21 PCLKI- Negative Parallel Clock, LVDS Input (Figure 1).
23, 25, 29, 31
PDI3+ to
PDI0+
Positive Data Inputs, LVDS (622Mbps or 666Mbps)
24, 26, 30, 32
PDI3- to
PDI0-
Negative Data Inputs, LVDS (622Mbps or 666Mbps)
34 PCLKO+ Positive Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz.
35 PCLKO- Negative Parallel Clock Output, LVDS. This clock may be 622.08MHz or 666MHz.
37 RCLK+ Positive Reference Clock Input, LVPECL
38 RCLK- Negative Reference Clock Input, LVPECL
39 CLKSET
Reference Clock Rate Programming Pin:
CLKSET = V
CC
; RCLK = 622.08MHz/666MHz
CLKSET = OPEN (float); RCLK = 155.52MHz/167MHz
CLKSET = 30kΩ to GND; RCLK = 77.76MHz/83.3MHz
CLKSET = GND; RCLK = 38.88MHz/41.6MHz
40 RATESET Data Rate Select, TTL Input. RATESET = high for 2.666Gbps, RATESET = low for 2.488Gbps.
41 VCCVCO
Supply Voltage for VCO +3.3V. Add bypass capacitors near this pin before connecting to the V
CC
power plane.
42 FIL PLL Capacitor Pin. Connect a 0.1µF capacitor from this pin to VCCVCO.
EP
Exposed
Paddle
The exposed paddle must be soldered to ground for proper thermal and electrical operation.
