Detailed Description
The MAX3892 converts 4-bit-wide, 622Mbps/667Mbps
data to 2.5Gbps/2.7Gbps serial data (Figure 2). Data is
loaded into the 4:1 MUX through a 4
✕ 4-bit FIFO buffer
for wide tolerance to clock skew. Clock and data inputs
are LVDS levels while high-speed serial outputs are
CML. An internal PLL frequency synthesizer generates
a serial clock from a low-speed reference clock.
Low-Voltage Differential-Signal
Inputs and Outputs
The MAX3892 has LVDS inputs and outputs for inter-
facing with high-speed digital circuitry. The LVDS stan-
dard is based on the IEEE 1596.3 LVDS specification.
This technology uses differential low-voltage swings to
achieve fast transition times, minimized power dissipa-
tion, and noise immunity. For proper operation, the par-
allel clock LVDS outputs (PCLKO+, PCLKO-) require
100Ω differential DC termination between the positive
and negative outputs. Do not terminate these outputs to
ground. The parallel data and parallel clock LVDS
inputs (PDI+, PDI-, PCLKI+, PCLKI-) are internally ter-
minated with 100Ω differential input resistance, and
therefore do not require external termination.
PECL Inputs
The reference clock (RCLK+, RCLK-) has PECL inputs
for interfacing to a crystal oscillator with AC or DC con-
nections. The RCLK inputs are self-biasing to V
CC
-
1.3V for AC-coupled inputs. Only a 100Ω differential
termination resistance must be added when inputs are
AC-coupled.
Current-Mode Logic Outputs
The 2.5Gbps/2.7Gbps data, clock, and system loop-
back outputs (SDO+, SDO-, SCLKO+, SCLKO-,
SLBO+, SLBO-) of the MAX3892 are designed using
current-mode logic (CML). The configuration of the
MAX3892 CML output circuit includes internal 50Ω
back termination to V
CC
(Figure 3). These outputs are
intended to drive a 50Ω transmission line terminated
with a matched load impedance.
FIFO Buffer
Data is latched into the MAX3892 by the parallel input
clock PCLKI. The parallel input clock serves as the
FIFO write clock. The parallel output clock PCLKO acts
as the FIFO read clock that loads the 4:1 MUX. The
FIFO allows the read and write clocks to vary by up to
±1UI. Conditions that result in the read and write clock
accessing the same FIFO address are indicated by
MAX3892
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
_______________________________________________________________________________________ 7
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLK0 = (PCLK0+) - (PCLKO-).
*PDI3 = D3; PDI2 = D2...PDI0 = D0. PDI3 IS THE MSB AND IS TRANSMITTED FIRST.
