REV. A
AD5582/AD5583
–15–
FFF
H
100 1k 10k 100k 1M 10M
800
H
001
H
000
H
400
H
200
H
100
H
080
H
040
H
020
H
010
H
008
H
004
H
002
H
FREQUENCY (Hz)
ATTENUATION (dB)
–96
–72
–48
–24
0
TPC 25. AD5582 Multiplying Bandwidth
Test Circuit
DAC
C
L
V
OUT
1k
1k
V
DD
Test Circuit 1
HOURS OF OPERATION AT 150C
0.8
0 100 600
ERROR (LSB)
–0.8
0
300
–0.6
0.4
–0.4
200
0.6
–0.2
0.2
V
DD
= +5V
V
SS
= –5V
V
REFH
= +4V
V
REFL
= –4V
400 500
+3
–3
+3
–3
GE DRIFT
ZSE DRIFT
TPC 26. AD5582 Long-Term Drift
THEORY OF OPERATION
The AD5582/AD5583 are quad, voltage output, 12-/10-bit parallel
input DACs in compact TSSOP-48 packages.
Each DAC is a voltage switching, high impedance (R = 20 kW),
R-2R ladder configuration with segmentation to optimize die
area and precision. Figure 3 shows a simplified R-2R structure
without the segmentation. The 2R resistances are switched
between V
REFH
and V
REFL
, and the output is obtained from
the rightmost ladder node. As the code is sequenced through
all possible states, the voltage of this node changes in steps of
(2/3 V
REFH
– V
REFL
)/(2
N
– 1) starting from the lowest V
REFL
and
going to the highest V
REFH
– DUTLSB. Buffering it with an
amplifier with a gain of 1.5 brings the output to:
V
D
VV V
OUT
N
REFH REFL REFL
=
()
+
()
21–
–
(1)
where D is the decimal equivalent of the data bits and N is the
numbers of bits.
If –V
REFL
is equal to V
REFH
as V
REF
, V
OUT
is simplified to:
V
D
V
OUT REF
=
Ê
Ë
Á
ˆ
¯
˜
2
4095
1–
(For AD5582) (2)
V
D
V
OUT REF
=
Ê
Ë
Á
ˆ
¯
˜
2
1023
1–
(For AD5583) (3)
The advantage of this scheme is that it allows the DAC to inter-
polate between two voltages for differential references or
single-ended reference.
These DACs feature double buffers, which allow both synchro-
nous and asynchronous channels update with additional data
readback capability. These parts can be reset to zero scale or mid-
scale controlled by the RS and MSB pins. When RS is activated,
the MSB of 0 resets the DACs to zero scale and the MSB of 1
resets the DACs to midscale. The ability to operate from wide
supply voltages, +5 V to +15 V or ± 5 V, with multiplying bipolar
references is another key feature of these DACs.
–
+
V
O
R
2R
2R
SW0
b0
2R
SW1
b1
2R
SW2
b2
2R
SWn–3
bn–2
2R
SWn–1
bn–1
2R
R R R
V
REFL
+
–
V
REFH
+
–
Figure 3. Simplified R-2R Architecture
(Segmentation Not Shown)
Power Supplies
There are three separate power supplies needed for the opera-
tion of the DACs. For dual supply, V
SS
can be set from –6.5 V
to –2.7 V and V
DD
can be set from +2.7 V to +6.5 V. For single
supply, V
SS
should be set at 0 V while V
DD
is set from 3 V to
16.5 V. However, setting the single supply of V
DD
below 4.5 V
can impact the overall accuracy of the device.
