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AD5582YRVZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
REV. A–4–
AD5582/AD5583
Parameter Symbol Condition Min Typ
1
Max Unit
LOGIC INPUTS/OUTPUTS
Logic Input Low Voltage V
IL
0.8 V
DV
DD
= 3 V ± 10% 0.4 V
Logic Input High Voltage V
IH
2.4 V
DV
DD
= 3 V ± 10% 2.1 V
Input Leakage Current I
IL
mA
Input Capacitance
4
C
IL
pF
Output Voltage High V
OH
I
OH
= –0.8 mA 2.4 V
Output Voltage Low V
OL
I
OL
= 1.2 mA, T
A
= 85C, 0.4 V
I
OL
= 0.6 mA, DV
DD
= 3 V
V
OL
I
OL
= 1.0 mA, T
A
= 125C, 0.4 V
I
OL
= 0.5 mA, DV
DD
= 3 V
AC CHARACTERISTICS
Output Slew Rate SR Data = Zero Scale to Full Scale 2 V/ms
to Zero Scale
Settling Time
8
t
S
To ± 0.1% of Full Scale 14 ms
DAC Glitch Q Code 7FF
H
to 800
H
to 7FF
H
for 100 nV-s
AD5582 and 1FF
H
to 200
H
to
1FF
H
for AD5583
Digital Feedthrough V
OUT
/t
CS
Data = Midscale, CS Toggles at 5 nV-s
f = 16 MHz
Analog Crosstalk V
OUT
/V
REF
V
REF
= 1.5 V dc + 1 V p-p, –80 dB
Data = 000
H
, f = 100 kHz
Output Noise e
N
f = 1 kHz 33 nV/÷Hz
SUPPLY CHARACTERISTICS
Single-Supply Voltage Range V
DD
V
SS
= 0 V 3 16.5 V
Dual-Supply Voltage Range V
DD
/V
SS
V
DD
= +2.7 V to +6.5 V, –6.5 +6.5 V
V
SS
= –6.5 V to –2.7 V
Digital Logic Supply DV
DD
2.7 6.5 V
Positive Supply Current
6
I
DD
V
IL
= 0 V, No Load 2.3 3.5 mA
Power Dissipation P
DISS
V
IL
= 0 V, No Load 34.5 52.5 mW
Power Supply Sensitivity PSS V
DD
= ± 5% 30 ppm/V
NOTES
1
Typical specifications represent average readings measured at 25∞C.
2
DAC Output Equation: V
OUT
= V
REFL
+ [(V
REFH
– V
REFL
) D/2
N
], where D = data in decimal loaded in corresponding DAC Register A, B, C, D, and N equals the number of
bits; AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V
REFH
– V
REFL
)/4096 V and = (V
REFH
– V
REFL
)/1024 V for AD5582 and AD5583, respectively.
3
The first two codes (000
H
, 001
H
) of the AD5583 and the first four codes (000
H
, 001
H
, 002
H
, 003
H
) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.
4
These parameters are guaranteed by design and not subject to production testing.
5
Dual-supply operation, V
REFL
= V
SS
, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.
6
Short circuit output and supply currents are 24 mA and 25 mA, respectively.
7
Part is stable under any capacitive loading conditions.
8
The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
(continued)
REV. A
AD5582/AD5583
–5–
TIMING CHARACTERISTICS
Parameter Symbol Condition Min Typ Max Unit
INTERFACE TIMING*
Chip Select Write Pulse Width t
WCS
35 ns
Chip Select Read Pulse Width t
RCS
130 ns
Write Setup t
WS
50 ns
Write Hold t
WH
0ns
Address Setup t
AS
50 ns
Address Hold t
AH
0ns
Load Setup t
LS
0ns
Load Hold t
LH
0ns
Write Data Setup t
WDS
50 ns
Write Data Hold t
WDH
0ns
Load Data Pulse Width t
LDW
35 ns
Reset Pulse Width t
RESET
35 ns
Read Data Hold t
RDH
0ns
Read Data Setup t
RDS
0ns
Data to Hi-Z t
DZ
C
L
= 10 pF 80 100 ns
Chip Select to Data t
CSD
C
L
= 10 pF 80 100 ns
Chip Select Repetitive Pulse Width t
CSP
20 ns
Load Setup in Double Buffer Mode t
LDS
35 ns
Load Data Hold t
LDH
0ns
*All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(V
DD
= 15 V or 5 V, V
SS
= 0 V, DV
DD
= 5 V 10%, V
REFH
= 10 V, V
REFL
= 0 V, –40C < T
A
< +125C,
unless otherwise noted.)
Parameter Symbol Condition Min Typ Max Unit
INTERFACE TIMING*
Chip Select Write Pulse Width t
WCS
20 ns
Chip Select Read Pulse Width t
RCS
130 ns
Write Setup t
WS
35 ns
Write Hold t
WH
0ns
Address Setup t
AS
35 ns
Address Hold t
AH
0ns
Load Setup t
LS
0ns
Load Hold t
LH
0ns
Write Data Setup t
WDS
35 ns
Write Data Hold t
WDH
0ns
Load Data Pulse Width t
LDW
20 ns
Reset Pulse Width t
RESET
20 ns
Read Data Hold t
RDH
0ns
Read Data Setup t
RDS
0ns
Data to Hi-Z t
DZ
C
L
= 10 pF 100 ns
Chip Select to Data t
CSD
C
L
= 10 pF 100 ns
Chip Select Repetitive Pulse Width t
CSP
10 ns
Load Setup in Double Buffer Mode t
LDS
20 ns
Load Data Hold t
LDH
0ns
*All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.
(V
DD
= 15 V or 5 V, V
SS
= 0 V, DV
DD
= 3 V 10%, V
REFH
= 10 V, V
REFL
= 0 V, –40C < T
A
< +125C,
unless otherwise noted.)
REV. A–6–
AD5582/AD5583
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5582/AD5583 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –9 V
V
DD
to V
REF+
. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
V
REF–
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
V
REFH
to V
REFL
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
DV
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Logic Inputs to GND . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 24 mA
Thermal Resistance Junction to Ambient,
JA
. . . . . . 115∞C/W
ORDERING GUIDE
1
Resolution Temperature Package Package Container Top
Model (Bits) Range Description Option Quantity Marking
2
AD5582YRV-REEL
1
12 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5582Y
AD5583YRV-REEL 10 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5583Y
AD5582YRV
1
12 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5582Y
AD5583YRV 10 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5583Y
NOTES
1
The AD5582 contains 4116 transistors. The die size measures 108 mil 144 mil.
2
First row marking is shown in the table above. Second row marking contains date code in YYWW format. Third row marking contains the lot number.
Thermal Resistance Junction to Case,
JC
. . . . . . . . . . 42∞C/W
Maximum Junction Temperature (T
J
Max) . . . . . . . . . . 150∞C
Package Power Dissipation = (T
J
Max – T
A
)/
JA
Operating Temperature Range . . . . . . . . . . –40∞C to +125∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature
RV-48 (Soldering, 60 secs) . . . . . . . . . . . . . . . . . . . . 300∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD5582YRVZ

Mfr. #:
Buy AD5582YRVZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC Quad 12bit Parallel In
Lifecycle:
New from this manufacturer.
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