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14
PIXEL OUTPUT INTERFACES
Parallel Interface
The parallel pixel data interface uses these output-only
signals:
• FRAME_VALID
• LINE_VALID
• PIXCLK
• DOUT[11:0]
The parallel pixel data interface is disabled by default at
power up and after reset. It can be enabled by programming
R0x301A. Table 7 shows the recommended settings.
When the parallel pixel data interface is in use, the serial
data output signals can be left unconnected. Set
reset_register [bit 12 (R0x301A[12] = 1)] to disable the
serializer while in parallel output mode.
Output Enable Control
When the parallel pixel data interface is enabled, its
signals can be switched asynchronously between the driven
and High-Z under pin or register control, as shown in
Table 6.
Table 6. OUTPUT ENABLE CONTROL
OE_BAR Pin Drive Pins R0x301A[6] Description
1 0 Interface High-Z
X 1 Interface Driven
0 X Interface Driven
Configuration of the Pixel Data Interface
Fields in R0x301A are used to configure the operation of
the pixel data interface. The supported combinations are
shown in Table 7.
Table 7. CONFIGURATION OF THE PIXEL DATA INTERFACE
Serializer Disable
R0x301 A[12]
Parallel Enable
R0x301 A[7]
Description
0 0 Power up default
Serial pixel data interface and its clocks are enabled. Transitions to soft standby
are synchronized to the end of frames on the serial pixel data interface
1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface
and its clocks disabled to save power. Transitions to soft standby are
synchronized to the end of frames in the parallel pixel data interface
High Speed Serial Pixel Data Interface
The High Speed Serial Pixel (HiSPi) interface uses four
data lanes and one clock as output.
• SLVSC_P
• SLVSC_N
• SLVS0_P
• SLVS0_N
• SLVS1_P
• SLVS1_N
• SLVS2_P
• SLVS2_N
• SLVS3_P
• SLVS3_N
The HiSPi interface supports three protocols,
Streaming-S, Streaming-SP, and Packetized SP. The
streaming protocols conform to a standard video application
where each line of active or intra-frame blanking provided
by the sensor is transmitted at the same length. The
Packetized SP protocol will transmit only the active data
ignoring line-to-line and frame-to-frame blanking data.
These protocols are further described in the High-Speed
Serial Pixel (HiSPi) Interface Protocol Specification
V1.50.00.
The HiSPi interface building block is a unidirectional
differential serial interface with four data and one double
data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple
lanes. Figure 10 shows the configuration between the HiSPi
transmitter and the receiver.
The HiSPi interface building block is a unidirectional
differential serial interface with four data and one double
data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple
lanes. Figure 10 shows the configuration between the HiSPi
transmitter and the receiver.
