AR0331
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Table 29. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND LINEAR MODE (continued)
Definition Unit
Max
TypMinSymbolCondition
PLL Supply Current Streaming, 1080p60 IDD_PLL – 8 12 mA
SLVS Supply Current Streaming, 1080p60 IDD_SLVS – 9 13 mA
1. Operating currents are measured at the following conditions:
V
AA = VAA_PIX= VDD_PLL=2.8 V
VDD =VDD_IO= 1.8 V
V
DD_SLVS = 0.4 V
PLL Enabled and PIXCLK=74.25 MHz
T
A
= 25°C
Table 30. OPERATING CURRENT IN HiSPi (SLVS) OUTPUT AND HDR MODE
Definition Condition Symbol Min Typ
Max
Unit
Digital Operating Current Streaming, 2048x1536 30fps IDD – 317 358 mA
Analog Operating Current Streaming, 2048x1536 30fps IAA – 45 55 mA
Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX – 8 13 mA
PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL – 8 12 mA
SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS – 9 13 mA
Digital Operating Current Streaming, 1080p60 IDD – 323 358 mA
Analog Operating Current Streaming, 1080p60 IAA – 55 70 mA
Pixel Supply Current Streaming, 1080p60 IAA_PIX – 9 14 mA
PLL Supply Current Streaming, 1080p60 IDD_PLL – 8 12 mA
SLVS Supply Current Streaming, 1080p60 IDD_SLVS – 9 13 mA
1. Operating currents are measured at the following conditions:
VAA=VAA_PIX= VDD_PLL=2.8 V
VDD = VDD_IO= 1.8 V
VDD_SLVS = 0.4 V
PLL Enabled and PIXCLK=74.25 MHz
T
A
= 25°C
HiSPi Electrical Specifications
The ON Semiconductor AR0331 sensor supports both
SLVS and HiVCM HiSPi modes. Please refer to the
High-Speed Serial Pixel (HiSPi) Interface Physical Layer
Specification v2.00.00 for electrical definitions,
specifications, and timing information. The V
DD_SLVS
supply in this datasheet corresponds to V
DD_TX in the
HiSPi Physical Layer Specification. Similarly, V
DD is
equivalent to V
DD_HiSPi as referenced in the specification.
The DLL as implemented on AR0331 is limited in the
number of available delay steps and differs from the HiSPi
specification as described in this section.
Table 31. CHANNEL SKEW
(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data Rate = 480 Mbps; DLL set to 0)
Data Lane Skew in Reference to Clock
tCHSKEW1PHY −150 ps
Table 32. CLOCK DLL STEPS
(Measurement Conditions: VDD_HiSPi = 1.8 V; VDD_HiSPi_TX = 0.8 V; Data DLL set to 0)
Clock DLL Step 1 2 3 4
5
6
Delay at 660 Mbps 0.25 0.375 0.5 0.625 0.75 UI
Eye_opening at 660 Mbps 0.85 0.78 0.71 0.71 0.69 UI
1. The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0331.
