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TFA9872CUK/N1Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
NXP Semiconductors
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
TFA9872_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 12 April 2017
COMPANY PUBLIC 16 / 32
Symbol Parameter Conditions Min Typ Max Unit
square wave on VDDD, f
ripple
= 217
Hz, V
ripple
= 50 mV (p-p), maximum
PGA gain setting (30 dB)
- 70 - dB
sine wave on VDDD, f
ripple
= 20 Hz to
1 kHz, V
ripple
= 100 mV (RMS),
maximum PGA gain setting (30 dB)
- 70 - dB
PSRR power supply rejection ratio
sine wave on VDDD, f
ripple
= 1 kHz to
20 kHz, V
ripple
= 100 mV (RMS),
maximum PGA gain setting (30 dB)
- 60 - dB
V
O(offset)
output offset voltage % of Full Scale; PDM output only
(offset is removed on TDM output)
[5]
-10 - 10 %
[1] L
BST
= boost converter inductance; R
L
= load resistance; L
L
= load inductance (speaker).
[2] This parameter is not tested during production; the value is guaranteed by design and checked during product validation.
[3] Overload level at input; output is specified at 0 dBFS for TDM/PDM output max, or output limited at THD+N =1 % if reached before 0 dBFS; THD = 1 %.
[4] Overload level at input; output is specified at 0 dBFS for TDM/PDM output max, or output limited at THD+N = 1 % if reached before 0 dBFS; THD = 1 %.
[5] When using PDM output for Speaker-as-Microphone, PDM stream decimation shall be done in codec or AP running SAM software and it must include a
DC offset remover.
NXP Semiconductors
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
TFA9872_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 12 April 2017
COMPANY PUBLIC 17 / 32
11.3 I
2
S timing characteristics
Table 8. I
2
S bus interface characteristics; see Figure 4
All parameters are guaranteed for V
BAT
= 3.6 V; V
DDD
= 1.8 V; V
DDP
= V
BST
= 9.0 V, Adaptive Boost mode; L
BST
= 1 μH
[1]
;R
L
= 8 Ω
[1]
; L
L
= 44 μH
[1]
; f
i
= 1 kHz; f
s
= 48 kHz; T
amb
= 25 °C; default settings, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
s
sampling frequency on pin WS, audio mode
[2]
16 - 48 kHz
on pin WS, ultrasonic mode 96 - 192 kHz
f
clk
clock frequency on pin BCK, audio mode
[2]
32f
s
- 384f
s
kHz
on pin BCK, ultrasonic mode - - 96f
s
MHz
WS edge to BCK HIGH
[3]
10 - - nst
su
set-up time
DATA edge to BCK HIGH 10 - - ns
BCK HIGH to WS edge
[3]
10 - - nst
h
hold time
BCK HIGH to DATA edge 10 - - ns
[1] L
BST
= boost converter inductance; R
L
= load resistance; L
L
= load inductance.
[2] The I
2
S bit clock input (BCK) is used as a clock input for the amplifier and the DC-to-DC converter. Note that both the BCK and WS signals must be
present for the clock to operate correctly.
[3] This parameter is not tested during production; the value is guaranteed by design and checked during product validation.
BCK
FS
DATA
t
h
t
su
010aaa750
Figure 4. I
2
S timing
NXP Semiconductors
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
TFA9872_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 12 April 2017
COMPANY PUBLIC 18 / 32
11.4 I
2
C timing characteristics
Table 9. I
2
C-bus interface characteristics; see Figure 5
All parameters are guaranteed for V
BAT
= 3.6 V; V
DDD
= 1.8 V; V
DDP
= V
BST
= 9.0 V, Adaptive Boost mode; L
BST
= 1 μH
[1]
;R
L
= 8 Ω
[1]
; L
L
= 44 μH
[1]
; f
i
= 1 kHz; f
s
= 48 kHz; T
amb
= 25 °C; default settings, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
SCL
SCL clock frequency - - 400 kHz
t
LOW
LOW period of the SCL clock 1.3 - - μs
t
HIGH
HIGH period of the SCL clock 0.6 - - μs
t
r
rise time SDA and SCL signals
[2]
20 + 0.1 C
b
- - ns
t
f
fall time SDA and SCL signals
[2]
20 + 0.1 C
b
- - ns
t
HD;STA
hold time (repeated) START condition
[3]
0.6 - - μs
t
SU;STA
set-up time for a repeated START condition 0.6 - - μs
t
SU;STO
set-up time for STOP condition 0.6 - - μs
t
BUF
bus free time between a STOP and START
condition
1.3 - - μs
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - μs
t
SP
pulse width of spikes that must be
suppressed by the input filter
[4]
0 - 50 ns
C
b
capacitive load for each bus line - - 400 pF
[1] L
BST
= boost converter inductance; R
L
= load resistance; L
L
= load inductance.
[2] C
b
is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
[3] After this period, the first clock pulse is generated.
[4] To be suppressed by the input filter.
Figure 5. I
2
C timing
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TFA9872CUK/N1Z

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Manufacturer:
NXP Semiconductors
Description:
Audio Amplifiers TFA9872CUK/WLCSP42//N1/REEL 7 Q1 DP CIRCUIT ELEME
Lifecycle:
New from this manufacturer.
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