NXP Semiconductors
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
TFA9872_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 12 April 2017
COMPANY PUBLIC 19 / 32
11.5 PDM timing characteristics
Table 10. PDM interface characteristics; see Figure 6
All parameters are guaranteed for V
BAT
= 3.6 V; V
DDD
= 1.8 V; V
DDP
= V
BST
= 9.0 V, Adaptive Boost mode; L
BST
= 1 μH
[1]
;R
L
= 8 Ω
[1]
; L
L
= 44 μH
[1]
; f
i
= 1 kHz; f
s
= 48 kHz; T
amb
= 25 °C; default settings, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
f
clk
clock frequency - 3.072
[2]
- MHz
δ
clk
clock duty cycle 45 - 55 %
after clock HIGH 30 - - nst
h
hold time
after clock LOW 30 - - ns
after clock HIGH 30 - - nst
su
set-up time
after clock LOW 30 - - ns
[1] L
BST
= boost converter inductance; R
L
= load resistance; L
L
= load inductance.
[2] PDM Clock is 64xfs, with fs selected by AUDFS. Typical 3.072 Mhz is corresponding to f
s
= 48 kHz.
t
su(CLKH)
t
h(CLKH)
t
su(CLKL)
t
h(CLKL)
CLK
DATA
010aaa711
Figure 6. PDM timing
