NXP Semiconductors
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
TFA9872_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 12 April 2017
COMPANY PUBLIC 25 / 32
References
Outline
version
European
projection
Issue date
IEC JEDEC JEITA
SOT1459-3 - - -
sot1459-3_po
16-03-01
16-05-09
Unit
mm
max
nom
min
3.16 2.49
2.4 0.05 0.03
A
Dimensions (mm are the original dimensions)
WLCSP42: wafer level chip-scale package; 42 bumps; 3.13 x 2.46 x 0.525 mm (backside coating included) SOT1459-3
A
1
A
2
0.26 3.13 2.46 0.4
b D E e e
1
2.0
e
2
v w
0.02
3.10 2.43
0.365 0.365 0.215
Z
D1
Z
D2
Z
E2
0.245
Z
E1
y
0.330.20
0.565
0.485
0.525
0
scale
3 mm
detail X
X
C
y
654321
e
2
A
ball A1
index area
ball A1
index area
BE A
D
A
A
2
A
1
b
AC BØ v
CØ w
e
1
e
e
Z
D2
Z
E2
Z
E1
Z
D1
B
C
D
E
F
G
Note: Backside coating 25 µm
Figure 12. Package outline TFA9872CUK/N1 (WLCSP42)
NXP Semiconductors
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
TFA9872_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 12 April 2017
COMPANY PUBLIC 26 / 32
14 Soldering of WLCSP packages
14.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
14.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
14.3 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 1) than a SnPb process, thus reducing
the process window
Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 11.
Table 11. Lead-free process (from J-STD-020D)
Package reflow temperature (°C)
Volume (mm
3
)
Package thickness (mm)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 1.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 13.
NXP Semiconductors
TFA9872_SDS
High Efficiency Class-D Audio Amplifier with Speaker-as-Microphone
TFA9872_SDS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2017. All rights reserved.
Product short data sheet Rev. 1 — 12 April 2017
COMPANY PUBLIC 27 / 32
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
MSL: Moisture Sensitivity Level
Figure 13. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
14.3.1 Stand off
The stand off between the substrate and the chip is determined by:
The amount of printed solder on the substrate
The size of the solder land on the substrate
The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
14.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and
the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the
bumps after reflow can occur during the reflow process in bumps with high ratio of bump
diameter to bump height, i.e. low bumps with large diameter. No failures have been found
to be related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
14.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing
the chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.

TFA9872CUK/N1Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Audio Amplifiers TFA9872CUK/WLCSP42//N1/REEL 7 Q1 DP CIRCUIT ELEME
Lifecycle:
New from this manufacturer.
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