LTC3769
21
3769fa
For more information www.linear.com/LTC3769
APPLICATIONS INFORMATION
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
C
LP
, holds the voltage at the VCO input.
where the load on INTV
CC
can be very small. The external
Schottky or silicon diode should be carefully chosen such
that INTV
CC
never gets charged up much higher than its
normal regulation voltage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on-chip
(such as an INTV
CC
short to ground), the overtemperature
shutdown circuitry will shut down the LTC3769. When the
junction temperature exceeds approximately 170°C, the
overtemperature circuitry disables the INTV
CC
LDO, causing
the INTV
CC
supply to collapse and effectively shut down
the entire LTC3769 chip. Once the junction temperature
drops back to approximately 155°C, the INTV
CC
LDO turns
back on. Long term overstress (T
J
> 125°C) should be
avoided as it can degrade the performance or shorten
the life of the part.
Since the shutdown may occur at full load, beware that
the load current will result in high power dissipation in the
body diodes of the top MOSFETs. In this case, the PGOOD
output may be used to turn the system load off.
Phase-Locked Loop and Frequency Synchronization
The LTC3769 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter
and a voltage-controlled oscillator (VCO). This allows
the turn-on of the bottom MOSFET to be locked signal
applied to 180 degrees out-of-phase to the rising edge of
the external clock. The phase detector is an edge-sensitive
digital type that provides zero degrees phase shift between
the external and internal oscillators. This type of phase
detector does not exhibit false lock to harmonics of the
external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
OSC
, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than f
OSC
,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
Figure 5. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3769 F05
400
200
500
700
900
300
100
0
65 75 85 95 105 115
125
Typically, the external clock (on the PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
Note that the LTC3769 can only be synchronized to an
external clock whose frequency is within range of the
LTC3769’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro
-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro
-
nization. Although it is not required that the free-running
frequency be near external clock frequency
, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
