OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC3769MPUF#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
LTC3769
22
3769fa
For more information www.linear.com/LTC3769
APPLICATIONS INFORMATION
Table 1 summarizes the different states in which the FREQ
pin can be used.
Table 1.
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTV
CC
DC Voltage 535kHz
Resistor DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the LTC3769 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continue to be regulated. More cycles will be skipped when
V
IN
increases. Once V
IN
rises above V
OUT
, the loop keeps
the top MOSFET continuously on. The minimum on-time
for the LTC3769 is approximately 110ns.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent
-
age of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3769 circuits: 1) IC VBIAS current, 2) INTV
CC
regulator current, 3) I
2
R losses, 4) bottom MOSFET transi-
tion losses, 5) body diode conduction losses.
1. The VBIAS current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
2. INT
V
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from INTV
CC
to ground. The resulting dQ/dt is a current
out of INTV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of
the topside and bottom side MOSFETs.
3. DC I
2
R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board traces
and cause the efficiency to drop at high output currents.
4. Transition losses apply only to the bottom MOSFET(s),
and become significant only when operating at low
input voltages. Transition losses can be estimated from:
Transition Loss = (1.7)
V
OUT
3
V
IN
•
I
OUT(MAX )
• C
RSS
• f
5. Body diode conduction losses are more significant at
higher switching frequency. During the dead time, the loss
in the top MOSFET is I
OUT
• V
DS
, where V
DS
is around 0.7V.
At higher switching frequency, the dead time becomes a
good percentage of switching cycle and causes the ef
-
ficiency to drop.
LTC3769
23
3769fa
For more information www.linear.com/LTC3769
APPLICATIONS INFORMATION
Other hidden losses, such as copper trace and internal
battery resistances, can account for an additional efficiency
degradation in portable systems. It is very important to
include these system-level losses during the design phase.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ΔI
LOAD
• ESR, where ESR is the effective
series resistance of C
OUT
. ΔI
LOAD
also begins to charge
or discharge C
OUT
, generating the feedback error signal
that forces the regulator to adapt to the current change
and return V
OUT
to its steady-state value. During this
recovery time V
OUT
can be monitored for excessive over-
shoot or ringing, which would indicate a stability problem.
OPTI-LOOP
®
compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 10 circuit will
provide an adequate starting point for most applications.
The ITH series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
be selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap
-
propriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
The gain of the loop will be increased by increasing R
C
and the bandwidth of the loop will be increased by de-
creasing C
C
. If RC is increased by the same factor that C
C
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • C
LOAD
. Thus, a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume V
IN
= 12V (nominal),
V
IN
= 22V (max), V
OUT
= 24V, I
OUT(MAX)
= 4A, V
SENSE(MAX)
=
75mV, and f = 350kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. Tie the FREQ pin to GND, generat
-
LTC3769
24
3769fa
For more information www.linear.com/LTC3769
APPLICATIONS INFORMATION
ing 350kHz operation. The minimum inductance for 30%
ripple current is:
ΔI
L
=
V
IN
f •L
1−
V
IN
V
OUT
⎛
⎝
⎜
⎞
⎠
⎟
The largest ripple happens when V
IN
= 1/2V
OUT
= 12V,
where the average maximum inductor current is:
I
MAX
=
I
OUT(MAX)
•
V
OUT
V
IN
= 8A
A 6.8μH inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R
SENSE
≤
75mV
9.25A
= 0.008Ω
Choosing 1% resistors: R
A
= 5k and R
B
= 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Vishay Si7848BDP MOS
-
FET results in: R
DS(ON)
= 0.012Ω, C
MILLER
= 150pF.
At maximum input voltage with T (estimated) = 50°C:
P
MAIN
=
(24V –12V) 24V
(12V)
2
•(4A)
2
• 1+(0.005)(50°C – 25°C)
[ ]
• 0.012
+ (1.7)(24V)
3
4A
12V
(150pF)(350kHz)= 0.84W
C
OUT
is chosen to filter the square current in the output.
The maximum output current peak is:
I
OUT(PEAK)
= 8 • 1+
31%
2
⎛
⎝
⎜
⎞
⎠
⎟
= 9.3A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominates the ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 6. Figure 7 illustrates the current
waveforms present in the synchronous regulator operating
in the continuous mode. Check the following in your layout:
1. Put the bottom N-channel MOSFET MBOT and the top
N-channel MOSFET MTOP1 in one compact area with
C
OUT
.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
INTVCC
must return to the combined C
OUT
(–) terminals.
The path formed by the bottom N-channel MOSFET
and the capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the source terminals
of the bottom MOSFETs.
3. Does the LTC3769 VFB pin’s resistive divider connect to
the (+) terminal of C
OUT
? The resistive divider must be
connected between the (+) terminal of C
OUT
and signal
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur
-
rent input feeds from the input capacitor(s).
4. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE
+
and SENSE
–
should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the INTV
CC
decoupling capacitor connected close
to the IC, between the INTV
CC
and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
immediately
next to
the INTV
CC
and GND pins can help
improve noise performance substantially.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

LTC3769MPUF#TRPBF

Mfr. #:
Buy LTC3769MPUF#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 60V L IQ Sync Boost Cntr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet