LTC4267-1
10
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Using an LTC4267-1 for the power and signature inter-
face functions of a PD provides several advantages. The
LTC4267-1 current limit circuit includes an onboard 100V
power MOSFET. This low leakage MOSFET is specified to
avoid corrupting the 25k signature resistor while also sav-
ing board space and cost. In addition, the inrush current
limit requirement of the IEEE 802.3af standard can cause
large transient power dissipation in the PD. The LTC4267-1
is designed to allow multiple turn-on sequences without
overheating the miniature 16-lead package. In the event of
excessive power cycling, the LTC4267-1 provides thermal
overload protection to keep the onboard power MOSFET
within its safe operating area.
OPERATION
The LTC4267-1 PD interface has several modes of opera-
tion depending on the applied input voltage as shown in
Figure 1 and summarized in Table 1. These modes satisfy
the requirements defined in the IEEE 802.3af specification.
The input voltage is applied to the V
PORTN
pin and must
be negative relative to the V
PORTP
pin. Voltages in the data
sheet for the PD interface portion of the LTC4267-1 are
with respect to V
PORTP
while the voltages for the switch-
ing regulator are referenced to PGND. It is assumed that
PGND
is tied to P
OUT
. Note the use of different ground
symbols throughout the data sheet.
Table 1. LTC4267-1 Operational Mode
as a Function of Input Voltage
INPUT VOLTAGE
(V
PORTN
with RESPECT to V
PORTP
) LTC4267-1 MODE OF OPERATION
0V to –1.4V Inactive
–1.5V to –9.5V** 25k Signature Resistor Detection
–9.8V to –12.4V Classification Load Current Ramps up
from 0% to 100%
–12.5V to UVLO* Classification Load Current Active
UVLO* to –57V Power Applied to Switching Regulator
* V
PORTN
UVLO includes hysteresis.
Rising input threshold 36.0V
Falling input threshold –30.5V
** Measured at LTC4267-1 pin. The LTC4267-1 meets the IEEE 802.3af
10V minimum when operating with the required diode bridges.
Figure 1. Output Voltage, PWRGD and PD
Current as a Function of Input Voltage
DETECTION V1
CLASSIFICATION
UVLO
TURN-ON
UVLO
OFF
POWER
BAD
UVLO
OFF
UVLO
ON
UVLO
TURN-OFF
τ = R
LOAD
C1
PWRGD TRACKS
V
PORTN
DETECTION V2
–10
TIME
20
30
V
PORTN
(V)
40
50
10
TIME
20
30
P
OUT
(V)
40
50
10
TIME
20
30
PWRGD (V)
40
50
I
CLASS
PD CURRENT
I
LIM_LO
dV
dt
I
LIM_LO
C1
=
POWER
BAD
POWER
GOOD
DETECTION I
1
CLASSIFICATION
I
CLASS
DETECTION I
2
LOAD, I
LOAD
(UP TO I
LIM_HI
)
CURRENT
LIMIT, I
LIM_LO
42671 F01
I
CLASS
DEPENDENT ON R
CLASS
SELECTION
I
LIM_LO
= 140mA (NOMINAL), I
LIM_HI
= 375mA (NOMINAL)
I
1
=
V1 – 2 DIODE DROPS
25kΩ
I
LOAD
= (UP TO I
LIM_HI
)
V
OUT
R
LOAD
I
2
=
V2 – 2 DIODE DROPS
25kΩ
V
PORTP
PSE
I
IN
LTC4267-1
R9
R
CLASS
R
LOAD
V
OUT
C1
R
CLASS
PWRGD
P
OUT
PGND
V
PORTN
V
IN
TIME
VOLTAGES WITH RESPECT TO V
PORTP
LTC4267-1
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Series Diodes
The IEEE 802.3af-defined operating modes for a PD refer-
ence the input voltage at the RJ45 connector on the PD.
The PD must be able to accept power of either polarity
at each of its inputs, so it is common to install diode
bridges (Figure 2). The LTC4267-1 takes this into account
by compensating for these diode drops in the threshold
points for each range of operation. A similar adjustment
is made for the UVLO voltages.
Detection
During detection, the PSE will apply a voltage in the range
of 2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable as
a PD. With the terminal voltage in this range, the LTC4267-1
connects an internal 25k resistor between the V
PORTP
and
V
PORTN
pins. This precision, temperature compensated
resistor presents the proper signature to alert the PSE
that a PD is present and desires power to be applied. The
internal low-leakage UVLO switch prevents the switching
regulator circuitry from affecting the detection signature.
The LTC4267-1 is designed to compensate for the voltage
and resistance effects of the IEEE required diode bridge
.
The signature range extends below the IEEE range to ac-
commodate the voltage drop of the two diodes. The IEEE
specification requires the PSE to use a V/I measurement
technique to keep the DC offset of these diodes from af-
fecting the signature resistance measurement. However,
the diode resistance appears in series with the signature
resistor and must be included in the overall signature
resistance of the PD. The LTC4267-1 compensates for
the two series diodes in the signature path by offsetting
the resistance so that a PD built using the LTC4267-1 will
meet the IEEE specification.
In some applications it is necessary to control whether
or not the PD is detected. In this case, the 25k signature
resistor can be enabled and disabled with the use of the
SIGDISA pin (Figure 3). Disabling the signature via the
SIGDISA pin will change the signature resistor to 9k
(typical) which is an invalid signature per the IEEE 802.3af
specification. This invalid signature is present for PD input
voltages from 2.8V to 10V. If the input rises above 10V,
the signature resistor reverts to 25k to minimize power
dissipation in the LTC4267-1. To disable the signature
,
tie
SIGDISA to V
PORTP
. Alternately, the SIGDISA pin can
be driven high with respect to V
PORTN
. When SIGDISA is
high, all functions of the PD interface are disabled.
RX
6
RX
+
3
TX
2
TX
+
RJ45
T1
POWERED DEVICE (PD)
INTERFACE
AS DEFINED
BY IEEE 802.3af
42671 F02
1
7
8
5
4
SPARE
SPARE
+
TO PHY
BR2
BR1
V
PORTP
8
4
D3
LTC4267-1
V
PORTN
Figure 2. LTC4267-1 PD Front End Using
Diode Bridges on Main and Spare Inputs
LTC4267-1
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Classification
Once the PSE has detected a PD, the PSE may option-
ally classify the PD. Classification provides a method for
more efficient allocation of power by allowing the PSE
to identify lower power PDs and allocate less power for
these devices. The IEEE 802.3af specification defines five
classes (Table 2) with varying power levels. The designer
selects the appropriate classification based on the power
consumption of the PD. For each class, there is an as-
sociated load current that the PD asserts onto the line
during classification probing. The PSE measures the PD
load current to determine the proper classification and PD
power requirements.
During classification (Figure 4), the PSE presents a fixed
voltage between –15.5V and –20.5V to the PD. With the
input voltage in this range, the LTC4267-1 asserts a load
current from the V
PORTP
pin through the R
CLASS
resistor.
The magnitude of the load current is set by the R
CLASS
resistor. The resistor values associated with each class
are shown in Table 2. Note that the switching regulator
will not interfere with the classification measurement since
the LTC4267-1 has not passed power to the regulator.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4267-1 R
CLASS
Resistor Selection
Class Usage
Maximum
Power Levels
at Input of PD
(W)
Nominal
Classification
Load Current
(mA)
LTC4267-1
R
CLASS
Resistor
(Ω, 1%)
0 Default 0.44 to 13.0 <5 Open
1 Optional 0.44 to 3.84 10.5 124
2 Optional 3.84 to 6.49 18.5 68.1
3 Optional 6.49 to 13.0 28 45.3
4 Reserved Reserved* 40 30.9
*Class 4 is currently reserved and should not be used.
The IEEE 802.3af specification limits the classification
time to 75ms because a significant amount of power is
dissipated in the PD. The LTC4267-1 is designed to handle
the power dissipation for this time period. If the PSE prob-
ing exceeds 75ms, the LTC4267-1 may overheat. In this
situation, the thermal protection circuit will engage and
disable the classification current source in order to protect
the part. The LTC4267-1 stays in classification mode until
the input voltage rises above the UVLO turn-on voltage.
V
PORTN
Undervoltage Lockout
The IEEE specification dictates a maximum turn-on voltage
of 42V and a minimum turn-off voltage of 30V for the PD.
In addition, the PD must maintain large on-off hysteresis to
prevent resistive losses in the wiring between the PSE and
the PD from causing start-up oscillation. The LTC
4267-1
incorporates
an undervoltage lockout (UVLO) circuit that
monitors the line voltage at V
PORTN
to determine when
to apply power to the integrated switching regulator
(Figure 5). Before the power is applied to the switching
regulator, the P
OUT
pin is high impedance and sitting at
the ground potential since there is no charge on capacitor
C1. When the input voltage rises above the UVLO turn-on
threshold, the LTC4267-1 removes the detection and clas-
sification loads and turns on the internal power MOSFET.
C1 charges up under the LTC4267-1 current limit control
and the P
OUT
pin transitions from 0V to V
PORTN
. This
sequence is shown in Figure 1. The LTC4267-1 includes
a hysteretic UVLO circuit on V
PORTN
that keeps power
applied to the load until the input voltage falls below the
UVLO turn-off threshold. Once the input voltage drops
below –30V, the internal power MOSFET is turned off and
Figure 4. IEEE 802.3af Classification Probing
Figure 3. 25k Signature Resistor with Disable
V
PORTP
V
PORTN
LTC4267-1
42671 F03
25k SIGNATURE
RESISTOR
SIGNATURE DISABLE
SIGDISA
9k
16k
TO
PSE
V
PORTP
R
CLASS
V
PORTN
LTC4267-1
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4267-1
42671 F04
R
CLASS
CURRENT PATH
V
PDPSE
PSE CURRENT MONITOR
PSE
PROBING
VOLTAGE
SOURCE
–15.5V TO –20.5V

LTC4267CGN-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE802.3af PD w/Switching Reg.
Lifecycle:
New from this manufacturer.
Delivery:
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