LTC4267CGN-1#TRPBF Datasheet LTC4267IGN-1#PBF, LTC4267CGN-1#PBF, LTC4267CGN-1#TRPBF | P19-P21

LTC4267-1

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can be disabled by floating the R

CLASS

pin. The R

CLASS

pin should not be shorted to V

PORTN

as this would force

the LTC4267-1 classification circuit to attempt to source

very large currents and quickly go into thermal shutdown.

Power Good Interface

The PWRGD signal is controlled by a high voltage, open-

drain transistor. The designer has the option of using this

signal to enable the onboard switching regulator through

the I

/RUN or the P

VCC

pins. Examples of active-high

interface circuits for controlling the switching regulator

are shown in Figure 7.

In some applications, it is desirable to ignore intermittent

power bad conditions. This can be accomplished by includ-

ing capacitor C15 in Figure 7 to form a lowpass filter. With

the components shown, power bad conditions less than

about 200µs will be ignored. Conversely, in other applica-

tions it may be desirable to delay assertion of PWRGD to

the switching regulator using C

PVCC

as shown in Figure 7.

It is recommended that the designer use the power good

signal to enable the switching regulator. Using PWRGD

ensures the capacitor C1 has reached within 1.5V of the

final value and is ready to accept a load.

The LTC4267-1

designed with wide power good hysteresis to handle

sudden fluctuations in the load voltage and current without

prematurely shutting off the switching regulator. Please

refer to the Power-Up Sequencing of the Application

Information section.

Signature Disable Interface

To disable the 25k signature resistor, connect SIGDISA pin

to the V

PORTP

pin. Alternately, SIGDISA pin can be driven

high with respect to V

PORTN

. An example of a signature

disable interface is shown in Figure 16, option 2. Note that

the SIGDISA input resistance is relatively large and the

threshold voltage is fairly low. Because of high voltages

present on the printed circuit board, leakage currents from

the V

PORTP

pin could inadvertently pull SIGDISA high. To

ensure trouble-free operation, use high voltage layout

techniques in the vicinity of SIGDISA. If unused, connect

SIGDISA to V

PORTN

Load Capacitor

The IEEE 802.3af specification requires that the PD main-

tain a minimum load capacitance of 5µF (provided by C1

in Figure 11). It is permissible to have a much larger load

capacitor and the LTC4267-1 can charge very large load

capacitors before thermal issues become a problem. The

load capacitor must be large enough to provide sufficient

energy for proper operation of

the switching

regulator.

However, the capacitor must not be too large or the PD

design may violate IEEE 802.3af requirements.

If the load capacitor is too large, there can be a problem

with inadvertent power shutdown by the PSE. Consider

the following scenario. If the PSE is running at –57V

(maximum allowed) and the PD has detected and powered

up, the load capacitor will be charged to nearly –57V. If

for some reason the PSE voltage is suddenly reduced to

–44V (minimum allowed), the input bridge will reverse bias

and the PD power will be supplied by the load capacitor.

Depending on the size of the load capacitor and the DC load

of the PD, the PD will not draw any power for a period of

time. If this period of time exceeds the IEEE 802.3af 300ms

disconnect delay, the PSE will remove power from the PD.

For this reason, it is necessary to ensure that inadvertent

shutdown cannot occur.

Very small output capacitors (≤10µF) will charge very

quickly in current limit. The rapidly changing voltage at

the output may reduce the current limit temporarily, caus-

ing the capacitor to charge at a somewhat reduced rate.

Conversely

, charging a very large capacitor may cause the

current limit to increase slightly. In either case, once the

output voltage reaches its final value, the input current

limit will be restored to its nominal value.

The load capacitor can store significant energy when fully

charged. The design of a PD must ensure that this energy

is not inadvertently dissipated in the LTC4267-1. The

polarity-protection diode(s) prevent an accidental short on

the cable from causing damage. However, if the V

PORTN

pin is shorted to V

PORTP

inside the PD while the capacitor

is charged, current will flow through the parasitic body

diode of the internal MOSFET and may cause permanent

damage to the LTC4267-1.

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Maintain Power Signature

In an IEEE 802.3af system, the PSE uses the maintain

power signature (MPS) to determine if a PD continues to

require power. The MPS requires the PD to periodically

draw at least 10mA and also have an AC impedance less

than 26.25kΩ in parallel with 0.05µF. If either the DC

current is less than 10mA or the AC impedance is above

26.25kΩ, the PSE may disconnect power. The DC current

must be less than 5mA and the AC impedance must be

above 2MΩ to guarantee power will be removed.

Selecting Feedback Resistor Values

The regulated output voltage of the switching regulator is

determined by the resistor divider across V

OUT

(R1 and

R2 in Figure 11) and the error amplifier reference voltage

REF

. The ratio of R2 to R1 needed to produce the desired

voltage can be calculated as:

R2 = R1 • (V

OUT

– V

REF

)/V

REF

In an isolated power supply application, V

REF

is determined

by the designer’s choice of an external error amplifier.

Commercially available error amplifiers or programmable

shunt regulators may include an internal reference of

1.25V or 2.5V. Since the LTC4267-1 internal reference

and error amplifier are not used

in an isolated design, tie

the V

pin to PGND.

In a nonisolated power supply application, the LTC4267-1

onboard internal reference and error amplifier can be

used. The resistor divider output can be tied directly to

the V

pin. The internal reference of the LTC4267-1 is

0.8V nominal.

Choose resistance values for R1 and R2 to be as large as

possible to minimize any efficiency loss due to the static

current drawn from V

OUT

, but just small enough so that

when V

OUT

is in regulation, the error caused by the nonzero

input current from the output of the resistor divider to the

error amplifier pin is less than 1%.

Error Amplifier and Opto-Isolator Considerations

In an isolated topology, the selection of the external error

amplifier depends on the output voltage of the switching

regulator. Typical error amplifiers include a voltage refer-

ence of either 1.25V or 2.5V. The output of the amplifier

and the amplifier upper supply rail are often tied together

internally. The supply rail is usually specified with a wide

upper voltage range, but it is not allowed to fall below the

reference voltage. This can be a problem in an isolated

switcher design if

the amplifier supply voltage is not prop-

erly

managed. When the switcher load current decreases

and the output voltage rises, the error amplifier responds

by pulling more current through the LED. The LED voltage

can be as large as 1.5V, and along with R

LIM

, reduces the

supply voltage to the error amplifier. If the error amp does

not have enough headroom, the voltage drop across the

LED and R

LIM

may shut the amplifier off momentarily,

causing a lock-up condition in the main loop. The switcher

will undershoot and not recover until the error amplifier

releases its sink current. Care must be taken to select the

reference voltage and R

LIM

value so that the error amplifier

always has enough headroom. An alternate solution that

avoids these problems is to utilize the LT1431 or LT4430

where the output of the error amplifier and amplifier supply

rail are brought out to separate pins.

The PD designer must also select an opto-isolator such

that its bandwidth is sufficiently wider than the bandwidth

of the main control loop. If this step is overlooked, the

main control loop may be difficult to stabilize. The output

collector resistor of the opto-isolator

can be selected for

an increase in bandwidth at the cost of a reduction in gain

of this stage.

Output Transformer Design Considerations

Since the external feedback resistor divider sets the

output voltage, the PD designer has relative freedom in

selecting the transformer turns ratio. The PD designer

can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)

which yields more freedom in setting the total turns and

mutual inductance and may allow the use of an off the

shelf transformer.

Transformer leakage inductance on either the primary or

secondary causes a voltage spike to occur after the output

switch (Q1 in Figure 11) turns off. The input supply volt-

age plus the secondary-to-primary referred voltage of the

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flyback pulse (including leakage spike) must not exceed

the allowed external MOSFET breakdown rating. This spike

is increasingly prominent at higher load currents, where

more stored energy must be dissipated. In some cases,

a “snubber” circuit will be required to avoid overvoltage

breakdown at the MOSFET’s drain node. Application

Note 19 is a good reference for snubber design.

Current Sense Resistor Consideration

The external current sense resistor (R

SENSE

in Figure 11)

allows the designer to optimize the current limit behavior

for a particular application. As the current sense resistor

is varied from several ohms down to tens of milliohms,

peak swing current goes from a fraction of an ampere to

several amperes. Care must be taken to ensure proper

circuit operation, especially for small current sense resis-

tor values.

Choose R

SENSE

such that the switching current exercises

the entire range of the I

/RUN voltage. The nominal voltage

range is 0.7V to 1.9V and R

SENSE

can be determined by

experiment. The main loop can be temporarily stabilized by

connecting a large capacitor on the power supply. Apply

the maximum load current allowable at the power sup-

ply output based on the class of the PD. Choose

SENSE

such that I

/RUN approaches 1.9V. Finally, exercise the

output load current over the entire operating range and

ensure that I

/RUN voltage remains within the 0.7V to

1.9V range. Layout is critical around the R

SENSE

resistor.

For example, a 0.020Ω sense resistor, with one milliohm

(0.001Ω) of parasitic resistance will cause a 5% reduction

in peak switch current. The resistance of printed circuit

copper traces cannot necessarily be ignored and good

layout techniques are mandatory.

Programmable Slope Compensation

The LTC4267-1 switching regulator injects a ramping

current through its SENSE pin into an external slope

compensation resistor (R

in Figure 11). This current

ramp starts at zero after the NGATE pin has been high for

the LTC4267-1’s minimum duty cycle of 6%. The current

rises linearly towards a peak of 5µA at the maximum duty

cycle of 80%, shutting off once the NGATE pin goes low.

A series resistor (R

) connecting the SENSE pin to the

current sense resistor (R

SENSE

) develops a ramping volt-

age drop. From the perspective of the LTC4267-1 SENSE

pin, this ramping voltage adds to the voltage across the

sense resistor, effectively reducing the current comparator

threshold in proportion to duty cycle. This

stabilizes the

control

loop against subharmonic oscillation. The amount

of reduction in the current comparator threshold (ΔV

SENSE

)

can be calculated using the following equation:

∆V

SENSE

= 5µA • R

• [(Duty Cycle – 6%)/74%]

Note: The LTC4267-1 enforces 6% < Duty Cycle < 80%.

Designs not needing slope compensation may replace R

with a short-circuit.

Applications Employing a Third Transformer Winding

A standard operating topology may employ a third wind-

ing on the transformer’s primary side that provides power

to the LTC4267-1 switching regulator via its P

VCC

(Figure 11). However, this arrangement is not inherently

self-starting. Start-up is usually implemented by the use of

an external “trickle-charge” resistor (R

START

) in conjunc-

tion with the internal wide hysteresis undervoltage lockout

circuit that monitors the P

VCC

pin voltage.

START

is connected to V

PORTP

and supplies a current,

typically 100µA, to charge C

PVCC

. After some time, the

voltage on C

PVCC

reaches the P

VCC

turn-on threshold. The

LTC4267-1 switching regulator then turns on abruptly and

draws its normal supply current. The NGATE pin begins

switching and the external MOSFET (Q1) begins to deliver

power. The voltage on C

PVCC

begins to decline as the

switching regulator draws its normal supply current,

which

exceeds the delivery from R

START

. After some time, typically

tens of milliseconds, the output voltage approaches the

desired value. By this time, the third transformer winding

is providing virtually all the supply current required by the

LTC4267-1 switching regulator.

One potential design pitfall is under-sizing the value of

capacitor C

PVCC

. In this case, the normal supply current

drawn through P

VCC

will discharge C

PVCC

rapidly before the

third winding drive becomes effective. Depending on the

particular situation, this may result in either several off-on

cycles before proper operation is reached or permanent

relaxation oscillation at the P

VCC

node.

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LTC4267CGN-1#TRPBF

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Manufacturer:

Analog Devices Inc.

Description:

Power Switch ICs - POE / LAN IEEE802.3af PD w/Switching Reg.

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LTC4267CGN-1#TRPBF

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