ZL30402QCG1 Datasheet ZL30402QCG1 | P19-P21

ZL30402 Data Sheet

Zarlink Semiconductor Inc.

RefSel: Reference Source Select. The RefSel (pin 47) input selects the PRI (primary) or SEC (secondary) input

as the reference clock for the Core PLL. The logic level at this input is sampled by the rising edge of F8o.

RefAlign

: Reference Align. The RefAlign (pin 48) input controls phase realignment between the input reference

and the generated output clocks.

4.1.2 Status Pins

The ZL30402 has two dedicated status pins for indicating modes of operation. These pins are listed below:

LOCK. This output goes high when the core PLL is locked to the selected Acquisition PLL.

HOLDOVER - This output goes high when the Core PLL enters Holdover mode. The Core PLL will switch to

Holdover mode if the respective Acquisition PLL enters Holdover mode or if the mode select pins or bits are set to

Holdover (MS2, MS1 = 01).

4.2 Software Control

Software control is enabled by setting the HW pin to logic zero (HW = 0). In this mode all hardware control pins

(inputs) are disabled and status bits (outputs) are enabled. The ZL30402 has seventeen registers that provide all

the functionality available in Hardware control and in addition they offer advanced control and monitoring that is

only available in Software control (see Figure 6 "Hardware and Software Control options").

4.2.1 Control Bits

The ZL30402 has seven control bits as is shown in Figure 6 "Hardware and Software Control options". The first five

bits replace the five hardware control pins: MS2, MS1, FCS, RefSel and RefAlign

and the last two bits support

recovery from Auto Holdover mode: AHRD and MHR. These bits are described in section 3.2.4.

In addition to the Control bits shown in Figure 6 "Hardware and Software Control options", the ZL30402 has a

number of bits and registers that are accessed infrequently or during configuration only e.g., Phase Offset

Adjustment or Master Clock Frequency Calibration.

FCS Filtering Characteristic Phase Slope

0 Filter corner frequency set to 1.1 Hz.

This selection meets requirements of G.813 Option 1 and GR-1244 stratum 3

clocks.

41ns

in 1.326ms

1 Filter corner frequency set to 0.1 Hz.

This selection meets requirements of G.813 Option 2, GR-253 for SONET stratum 3

and GR-253 for SONET Minimum Clocks (SMC).

885ns/s

Table 2 - Filter Characteristic Selection

RefSel Input Reference

0 Core PLL connected to the Primary Acquisition PLL

1 Core PLL connected to the Secondary Acquisition PLL

Table 3 - Reference Source Select

ZL30402 Data Sheet

Zarlink Semiconductor Inc.

4.2.2 Status Bits

The ZL30402 has seven status bits (see Figure 6 "Hardware and Software Control options"). The first two bits

perform the same function as their equivalent status pins. The last five bits perform two functions. Bits FLIM, PAFL,

SAFL indicate drift of the reference clock frequencies beyond the capture range of Acquisition and Core PLLs and

bits PAH and SAH show entry of Primary and Secondary Acquisition PLLs into Holdover mode. These bits are

described in detail in section 3.2.4. The status pins are enabled when the ZL30402 operates in software control and

they can be used to trigger interrupts.

4.2.3 ZL30402 Register Map

Addresses: 00H to 6FH

Note: The ZL30402 uses address space from 00h to 6Fh. Registers at address locations not listed above must not be written or read.

Address

hex

Read

Write

Function

00 Control Register 1 R/W

RefSel, 0, 0, MS2, MS1, FCS, 0, RefAlign

01 Status Register 1 R

rsv, rsv, LOCK, HOLDOVER, rsv, FLIM, rsv, rsv

04 Control Register 2 R/W

E3DS3/OC3

, E3/DS3, 0, 0, 0, 0, 0, 0,

06 Phase Offset Register 2 R/W

0, 0, 0, 0, OffEn, C16POA10, C16POA9, C16POA8

07 Phase Offset Register 1 R/W

C16POA7, C16POA6, C16POA5, C16POA4, C16POA3,

C16POA2, C16POA1, C16POA0

0F Device ID Register R

0010 0001

11 Control Register 3 R/W

rsv, rsv, C1.5POA2, C1.5POA1, C1.5POA0, 0, 0, 0

13 Clock Disable Register 1 R/W

0, 0, C16dis, C8dis, C4dis, C2dis, C1.5dis,0

14 Clock Disable Register 2 R/W

0, 0, 0, F8odis, F0odis, F16odis, C6dis, C19dis

19 Core PLL Control Register R/W

0, 0, 0, 0, 0, 0, MHR, AHRD, 0

1A Fine Phase Offset Register R/W

FPOA7, FPOA6, FPOA5, FPOA4, FPOA3, FPOA2, FPOA1,

FPOA0

20 Primary Acquisition PLL Status

rsv, rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, PAH,PAFL

28 Secondary Acquisition PLL

Status Register

rsv, rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, SAH, SAFL

40 Master Clock Frequency

Calibration Register - Byte 4

R/W

MCFC31, MCFC30, MCFC29, MCFC28, MCFC27, MCFC26,

MCFC25, MCFC24,

41 Master Clock Frequency

Calibration Register - Byte 3

R/W

MCFC23, MCFC22, MCFC21, MCFC20, MCFC19, MCFC18,

MCFC17, MCFC16

42 Master Clock Frequency

Calibration Register - Byte 2

R/W

MCFC15, MCFC14, MCFC13, MCFC12, MCFC11, MCFC10,

MCFC9, MCFC8

43 Master Clock Frequency

Calibration Register - Byte 1

R/W

MCFC7, MCFC6, MCFC5, MCFC4, MCFC3, MCFC2, MCFC1,

MCFC0

Table 4 - ZL30402 Register Map

ZL30402 Data Sheet

Zarlink Semiconductor Inc.

4.2.4 Register Description

Address: 00 H

Bit Name Functional Description Default

7RefSel

Reference Select. A zero selects the PRI (Primary) reference source

as the input reference signal and a one selects the SEC (secondary)

reference.

6-5 RSV

Reserved.

4-3 MS2, MS1

Mode Select

- MS2 = 0 MS1 = 0 Normal Mode (Locked Mode)

- MS2 = 0 MS1 = 1 Holdover Mode

- MS2 = 1 MS1 = 0 Free-run Mode

- MS2 = 1 MS1 = 1 Reserved

2FCS

Filter Characteristic Select

FCS = 0 Filter corner frequency set to 1.1 Hz. This selection meets

requirements of G.813 Option 1 and GR-1244 stratum 3 clocks.

FCS = 1 Filter corner frequency set to 0.1 Hz. This selection meets

requirements of G.813 Option 2, GR-253 for SONET stratum 3 and

GR-253 for SONET Minimum Clocks (SMC).

1RSV

Reserved.

RefAlign

Reference Align. A high-to-low transition aligns the generated output

clocks to the input reference signal. The maximum phase slope

depends on the Filter Characteristic selected and is limited to:

- 41ns in 1.326ms for FCS = 0

- 885 ns in 1s for FCS = 1

Table 5 - Control Register 1 (R/W)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P44

ZL30402QCG1

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Phase Locked Loops - PLL Pb Free Sonet / SDH Network Element PLL

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ZL30402QCG1