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ZL30402QCG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
ZL30402 Data Sheet
25
Zarlink Semiconductor Inc.
Address: 14 H
Address: 19 H
Bit Name Functional Description Default
7-5 RSV Reserved. 000
4 F8odis F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 122 ns
active high framing pulse output.
0
3 F0odis F0o
Frame Pulse Disable. When set high, this bit tristates the 8 kHz 244 ns
active low framing pulse output.
0
2 F16odis F16o
Frame Pulse Disable. When set high, this bit tristates the 8 kHz 61 ns
active low framing pulse output.
0
1C6dis6.312 MHz Clock Disable. When set high, this bit tristates the 6.312 MHz clock
output.
0
0 C19dis 19.44 MHz Clock Disable. When set high, this bit tristates the 19.44 MHz clock
output.
0
Table 13 - Clock Disable Register 2 (R/W)
Bit Name Functional Description Default
7-3 RSV Reserved. 00000
2MHRManual Holdover Release. A change form 0 to 1 on the MHR bit will release the Core
PLL from Auto Holdover to Normal when automatic return from Holdover is disabled
(AHRD is set to 1). This bit is level sensitive and it must be cleared immediately after it
is set to 1 (next write operation). This bit has no effect if AHRD is set to 0.
0
1 AHRD Automatic Holdover Return Disable. When set high, this bit inhibits the Core PLL
from automatically switching back to Normal mode from Auto Holdover state when the
active Acquisition PLL regains lock to input reference. The active Acquisition PLL is the
Acquisition PLL to which the Core PLL is currently connected.
0
0RSVReserved. 0
Table 14 - Core PLL Control Register (R/W)
ZL30402 Data Sheet
26
Zarlink Semiconductor Inc.
Address: 1A H
Address: 20 H
Bit Name Functional Description Default
7-0 FPOA7 - 0 Fine Phase Offset Adjustment. This register allows phase offset adjustment of
all output clocks and frame pulses (C
16o, C8o, C4o, C2o, F16o, F8o, F0o, C155,
C19o, C34/44, C1.5o, C6o) relative to the active input reference. The adjustment
can be positive (advance) or negative (delay) with a nominal step size of 477 ps
(61.035 ns / 128). The rate of phase change is limited to 885 ns/s for FCS = 1 and
41 ns in 1.326 ms for FCS = 0 selections. The phase offset value is a signed 2’s
complement number e.g.:
Advance: +1 step = 01H, +2 steps = 02H, +127 steps = EFH
Delay: -1 step = FFH, -2 steps = FEH, -128 steps = 80H
Example: Writing 08H advances all clocks by 3.8 ns and writing F3H delays all
clocks
00000
000
Table 15 - Fine Phase Offset Register (R/W)
Bit Name Functional Description
7-5 RSV Reserved.
4-3 InpFreq1-
0
Input Frequency. These two bits identify the Primary Reference Clock frequency.
- 00 = 19.44 MHz
- 01 = 8 kHz
- 10 = 1.544 MHz
- 11 = 2.048 MHz
2RSVReserved.
1PAHPrimary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL
enters Holdover mode. Holdover mode is entered when the reference frequency is
- lost completely
- drifts more than ±30 000 ppm off from the nominal frequency
- a large phase hit occurs on the reference clock.
0PAFLPrimary Acquisition PLL Frequency Limit. This bit goes high whenever the Acquisition
PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large
excursion of still tolerable input jitter.
Table 16 - Primary Acquisition PLL Status Register (R)
ZL30402 Data Sheet
27
Zarlink Semiconductor Inc.
Address: 28 H
Address: 40 H
Address: 41 H
Address: 42 H
Bit Name Functional Description
7-5 RSV Reserved.
4-3 InpFreq1-0 Input Frequency. These two bits identify the Secondary Reference Clock frequency.
- 00 = 19.44 MHz
- 01 = 8 kHz
- 10 = 1.544 MHz
- 11 = 2.048 MHz
2RSVReserved.
1 SAH Secondary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL
enters Holdover mode. Holdover mode is entered when reference frequency is:
- lost completely
- drifts more than ±30 000 ppm off the nominal frequency
- a large phase hit occurs on the reference clock.
0 SAFL Secondary Acquisition PLL Frequency Limit. This bit goes high whenever the Acquisition
PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large
excursion of still tolerable input jitter.
Table 17 - Secondary Acquisition PLL Status Register (R)
Bit Name Functional Description Default
7-0 MCFC31 - 24 Master Clock Frequency Calibration. This most significant byte contains the
31st to 24th bit of the Master Clock Frequency Calibration Register. See
Applications section 4.2 for a detailed description of how to calculate the MCFC
value.
00000
000
Table 18 - Master Clock Frequency Calibration Register 4 (R/W)
Bit Name Functional Description Default
7-0 MCFC23 - 16 Master Clock Frequency Calibration. This byte contains the 23rd
to 16th bit of the Master Clock Frequency Calibration Register.
00000
000
Table 19 - Master Clock Frequency Calibration Register 3 (R/W)
Bit Name Functional Description Default
7-0 MCFC15 - 8 Master Clock Frequency Calibration. This byte contains the 15th
to 8th bit of the Master Clock Frequency Calibration Register.
00000
000
Table 20 - Master Clock Frequency Calibration Register 2 (R/W)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

ZL30402QCG1

Mfr. #:
Buy ZL30402QCG1
Manufacturer:
Microchip / Microsemi
Description:
Phase Locked Loops - PLL Pb Free Sonet / SDH Network Element PLL
Lifecycle:
New from this manufacturer.
Delivery:
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