ZL30402QCG1 Datasheet ZL30402QCG1 | P31-P33

ZL30402 Data Sheet

Zarlink Semiconductor Inc.

5.1.4 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL

The NORMAL to HOLDOVER to NORMAL mode switching is usually performed when:

• A reference clock is available but its frequency drifts beyond some specified limit. In a Network Element with

stratum 3 internal clocks, the reference failure is declared when its frequency drifts more than ±12 ppm

beyond its nominal frequency.

• During routine maintenance of equipment when orderly switching of reference clocks is possible. This may

happen when synchronization references must be rearranged or when a faulty line card must be replaced.

Figure 10 - Manual Reference Switching

Two types of transitions are possible:

• Semi-automatic transition, which involves changing RefSel input to select a secondary reference clock

without changing the mode select inputs MS2, MS1 = 00 (Normal mode). This forces ZL30402 to

momentarily transition through the Holdover state and automatically return to Normal mode after

synchronizing to a secondary reference clock.

• Manual transition, which involves switching into Holdover mode (MS2, MS1 = 01), changing references with

RefSel, and manual return to the Normal mode (MS2, MS1 = 00).

In both cases, the change of references provides “hitless” switching.

5.2 Programming Master Clock Oscillator Frequency Calibration Register

The Master Crystal Oscillator and its programmable Master Clock Frequency Calibration register (see Table 18,

Table 19, Table 20, and Table 21) have been described in Section 3.0 "Master Clock Frequency Calibration Circuit",

on page 16. Programming of this register should be done after system has been powered long enough for the

Master Crystal Oscillator to reach a steady operating temperature. When the temperature stabilizes the crystal

oscillator frequency should be measured with an accurate frequency meter. The frequency measurement should be

substituted for the f

offset

variable in the following equation.

MCFC = 45036 * ( - f

offset

)

where f

offset

is the crystal oscillator frequency offset from the nominal 20 000 000 Hz frequency expressed in Hz.

NORMAL

(LOCKED)

AUTO

HOLD-

OVER

HOLD-

OVER

FREE-

RUN

RESET

Ref: OK &

MS2, MS1 == 00

{AUTO}

Ref: OK --> FAIL &

MS2, MS1 == 00

{AUTO}

MS2, MS1 == 01 OR

RefSel change Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=1 &

MHR= 0-->1 then 1-->0

{MANUAL}

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=0

{AUTO}

MS2, MS1 == 10 forces

unconditional return from

any state to Free-run

MS2, MS1! = 10

RESET

== 1

RefSel Change

ZL30402 Data Sheet

Zarlink Semiconductor Inc.

Example 1: Calculate the binary value that must be written to the MCFC register to correct a -1ppm offset of the

Master Crystal Oscillator. The -1ppm offset for a 20 MHz frequency is equivalent to -20 Hz:

MCFC = 45036 * 20 = 900720 = 00 0D BE 70 H

Note: Correcting the -1ppm crystal offset requires +1ppm MCFC offset.

Example 2: Calculate the binary value that must be written to the MCFC register to correct a +2 ppm offset of the

Master Crystal Oscillator. The +2 ppm offset for 20 MHz frequency is equivalent to 40 Hz:

MCFC = 45036 * (-40) = -1801440 = FF E4 83 20 H

6.0 Characteristics

6.1 AC and DC Electrical Characteristics

* Voltages are with respect to ground (GND) unless otherwise stated

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

* Voltages are with respect to ground (GND) unless otherwise stated

Absolute Maximum Ratings*

Parameter Symbol Min. Max. Units

1 Supply voltage V

DDR

-0.3 7.0 V

2 Voltage on any pin V

-0.3 VDD+0.3 V

3 Current on any pin I

30 mA

4 Storage temperature T

-55 125 °C

5 Package power dissipation (80 pin LQFP) P

1000 mW

6 ESD rating V

ESD

1500 V

Recommended Operating Conditions*

Characteristics Symbol Min. Typ. Max. Units

1 Supply voltage V

3.0 3.3 3.6 V

2 Operating temperature T

-40 25 +85 °C

ZL30402 Data Sheet

Zarlink Semiconductor Inc.

* Voltages are with respect to ground (GND) unless otherwise stated

Note 1: V

is defined as (V

+ V

) / 2

Note 2: Rise and fall times are measured at 20% and 80% levels.

* Voltages are with respect to ground (GND) unless otherwise stated

* Supply voltage and operating temperature are as per Recommended Operating Conditions

* Timing for input and output signals is based on the worst case conditions (over T

and V

)

Figure 11 - Timing Parameters Measurement Voltage Levels

DC Electrical Characteristics*

Characteristics Symbol Min. Max. Units Notes

1 Supply current with C20i = 20 MHz I

135 mA Outputs unloaded

2 Supply current with C20i = 0V I

DDS

2.2 mA Outputs unloaded

3 CMOS high-level input voltage V

CIH

0.7V

4 CMOS low-level input voltage V

CIL

0.3V

5 Input leakage current I

15 µAV

or GND

6 High-level output voltage V

2.4 V I

=10 mA

7 Low-level output voltage V

0.4 V I

=10 mA

8 LVDS: Differential output voltage V

250 450 mV Z

=100 Ω

9 LVDS: Change in VOD between

complementary output states

50 mV Z

=100 Ω

10 LVDS: Offset voltage V

1.125 1.375 V Note 1

11 LVDS: Change in VOS between

complementary output states

50 mV

12 LVDS: Output short circuit current I

24 mA Pin short to GND

13 LVDS: Output rise and fall times T

260 900 ps Note 2

AC Electrical Characteristics - Timing Parameter Measurement - CMOS Voltage Levels*

Characteristics Symbol Level Units

1 Threshold voltage V

0.5V

2 Rise and fall threshold voltage High V

0.7V

3 Rise and fall threshold voltage Low V

0.3V

ALL SIGNALS

Timing Reference Points

IF,

IR,

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P44

ZL30402QCG1

Mfr. #:

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Description:

Phase Locked Loops - PLL Pb Free Sonet / SDH Network Element PLL

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