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ZL30402QCG1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
ZL30402 Data Sheet
22
Zarlink Semiconductor Inc.
Address: 01 H
Address: 04 H
Bit Name Functional Description
7RSVReserved.
6RSVReserved.
5LOCKLock. This bit goes high when the Core PLL is locked to the selected Acquisition
PLL.
4 HOLDOVER Holdover. This bit goes high when the Core PLL enters Holdover mode. Detection
of reference failure and subsequent transition from Normal to Holdover state takes
approximately: 0.750 µs for 19.44 MHz reference, 0.850 µs for 2.048 MHz
reference, 1.1 µs for 1.544 MHz reference and 130 µs for 8 kHz reference.
3RSVReserved.
2FLIMFrequency Limit. This bit goes high when the Core PLL is pulled by the input
reference signal to the edge of its frequency tracking range set at ±104 ppm. This
bit may change state momentarily in the event of large jitter or wander excursions
occurring when the input reference is close to the frequency limit range.
1RSVReserved.
0RSVReserved.
Table 6 - Status Register 1 (R)
Bit Name Functional Description Default
7 E3DS3/OC3
E3, DS3 or OC-3 clock select. Setting this bit to zero enables the
C155P/N outputs (pin 30 and pin 31) and enables the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high sets the C155 clock
outputs into high impedance and enables the C34/C44 output to
provide a C34 or C44 clock.
0
6E3/DS3
E3 or DS3 clock select. When E3DS3/OC3 bit is set high, a logic
low on the E3/DS3
bit selects a 44.736 MHz clock on the C34/C44
output and logic high selects a 34.368 MHz clock. When the
E3DS3/OC3
bit is set low, a logic low on the E3/DS3 bit selects an
11.184 MHz clock on the C34/C44 output and a logic high selects
an 8.592 MHz clock.
0
5-0 RSV Reserved. 000000
Table 7 - Control Register 2 (R/W)
ZL30402 Data Sheet
23
Zarlink Semiconductor Inc.
Address: 06 H
Address: 07 H
Address: 0F H
Bit Name Functional Description Default
7-4 RSV
Reserved.
0000
3OffEn
Offset Enable. Set high to enable programmable phase offset
adjustments (C16 Phase Offset Adjustment and C1.5 Phase Offset
Adjustment) between the input reference and the generated clocks.
0
2 - 0 C16POA10
to
C16POA8
C16 Phase Offset Adjustment. These three bits (most significant) in
conjunction with the eight bits of Phase Offset Register 1 allow for
phase shifting of all clocks and frame pulses that are derived from the
C16
clock (C8o, C4o, C2o, F16o, F8o, F0o). The phase offset is an
unsigned number in a range from 0 to 2047. Each increment by one
represents phase-offset advancement by 61.035 ns with respect to
the input reference signal. The phase offset is a two-byte value and it
must be written in one step increments. For example: four writes are
required to advance clocks by 244 ns from its current position of 22H:
write 23H, 24H, 25H, 26H. Writing numbers in reverse order will delay
clocks from their present position.
000
Table 8 - Phase Offset Register 2 (R/W)
Bit Name Functional Description Default
7-0 C16POA7
to
C16POA0
C16 Phase Offset Adjustment. The eight least significant bits of the
phase offset adjustment word. See the Phase Offset Register 2 for
details.
0000
0000
Table 9 - Phase Offset Register 1 (R/W)
Bit Name Functional Description
7-4 ID7 - 4 Device Identification Number. These four bits represent the device part number.
The ID number for ZL30402 is 0010.
3-0 ID3 - 0 Device Revision Number. These bits represent the revision number. Number
starts from 0001.
Table 10 - Device ID Register (R)
ZL30402 Data Sheet
24
Zarlink Semiconductor Inc.
Address: 11 H
Address: 13 H
Bit Name Functional Description Default
7RSVReserved. 0
6RSVReserved. 0
5-3 C1.5POA2
to
C1.5POA0
C1.5 Phase Offset Adjustment. These three bits allow for changing of
the phase offset of the C1.5o clock relative to the active input reference.
The phase offset is an unsigned number in a range from 0 to 7. Each
increment by one represents phase-offset advancement by 80.96 ns.
Example: Writing 010 advances C1.5 clock by 162 ns. Successive writing
of 001 delays this clock by 80.96 ns from its present position
000
2-0 RSV Reserved. 000
Table 11 - Control Register 3 (R/W)
Bit Name Functional Description Default
7RSVReserved. 0
6RSVReserved. 0
5 C16dis 16.384 MHz Clock Disable. When set high, this bit tristates the 16.384 MHz clock
output.
0
4C8dis8.192 MHz Clock Disable. When set high, this bit tristates the 8.192 MHz clock
output.
0
3C4dis4.096 MHz Clock Disable. When set high, this bit tristates the 4.096 MHz clock
output.
0
2C2dis2.048 MHz Clock Disable. When set high, this bit tristates the 2.048 MHz clock
output.
0
1 C1.5dis 1.544 MHz Clock Disable. When set high, this bit tristates the 1.544 MHz clock
output.
0
0RSVReserved. 0
Table 12 - Clock Disable Register 1 (R/W)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44

ZL30402QCG1

Mfr. #:
Buy ZL30402QCG1
Manufacturer:
Microchip / Microsemi
Description:
Phase Locked Loops - PLL Pb Free Sonet / SDH Network Element PLL
Lifecycle:
New from this manufacturer.
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