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X9252YV24IZ-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
1
FN8167.3
X9252
Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface
Quad Digitally-Controlled (XDCP™)
Potentiometer
The X9252 integrates 4 digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented
using 255 resistive elements in a series array. Between each
pair of elements are tap points connected to wiper terminals
through switches. The position of each wiper on the array is
controlled by the user through the Up/Down (U/D
) or 2-wire
bus interface. The wiper of each potentiometer has an
associated volatile Wiper Counter Register (WCR) and four
nonvolatile Data Registers (DRs) that can be directly written
to and read by the user. The contents of the WCR controls
the position of the wiper on the resistor array through the
switches. At power-up, the device recalls the contents of the
default data registers DR00, DR10, DR20, DR30, to the
corresponding WCR.
Each DCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including the programming of bias voltages, the
implementation of ladder networks, and three resistor
programmable networks.
Features
• Quad Solid State Potentiometer
• 256 Wiper Tap Points-0.4% Resolution
• 2-Wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Up/Down Interface for Individual Potentiometers
• Wiper Resistance: 40 Typical
• NonVolatile Storage of Wiper Positions
• Power On Recall. Loads Saved Wiper Position on
Power-Up.
• Standby Current < 100µA Max
• Maximum Wiper Current: 3mA
•V
CC
: 2.7V to 5.5V Operation
•2.8k and 10k Version of Total Pot Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
• 24 Ld TSSOP
• Pb-Free (RoHS Compliant)
Pinout
X9252
(24 LD TSSOP)
TOP VIEW
R
H2
R
H3
R
W2
1
2
3
4
5
6
7
14
20
19
18
17
16
15
DS0
DS1
A0
R
W3
U/D
R
L3
SCL
R
L2
V
SS
R
L1
R
W0
CS
R
H0
R
L0
R
W1
R
H1
V
CC
8
9
10
13
WP
A2
11
12
SDA
A1
24
23
22
21
Data Sheet July 24, 2014
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Copyright Intersil Americas LLC 2005, 2014. All Rights Reserved
Intersil (and design) and
XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
2
FN8167.3
July 24, 2014
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Functional Diagram
Ordering Information
PART
NUMBER
(Notes 1
, 2)
PART
MARKING
R
TOTAL
(k)
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
X9252YV24IZ-2.7 X9252YV ZG 2.8 -40 to +85 24 Ld TSSOP (4.4mm) M24.173
X9252WV24IZ-2.7 X9252WV ZG 10 -40 to +85 24 Ld TSSOP (4.4mm) M24.173
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for X9252
. For more information on MSL please see tech brief TB363
POWER-UP,
INTERFACE
CONTROL
AND
V
CC
V
SS
2-Wire
R
H0
R
L0
DCP0
R
W0
A1
SDA
SCL
CS
U/D
A2
DS0
DS1
WP
WCR0
DR00
DR01
DR02
DR03
R
H1
R
L1
DCP1
R
W1
WCR1
DR10
DR11
DR12
DR13
R
H2
R
L2
DCP2
R
W2
WCR2
DR20
DR21
DR22
DR23
R
H3
R
L3
DCP3
R
W3
WCR3
DR30
DR31
DR32
DR33
A0
Interface
Up-Down
Interface
STATUS
Pin Descriptions
PIN # SYMBOL DESCRIPTION
1, 24 DS0, DS1 DCP select for Up/Down interface.
2, 14, 11 A0, A1, A2 Device address for 2-wire bus.
3R
W3
Wiper terminal of DCP3.
4R
H3
High terminal of DCP3.
5R
L3
Low terminal of DCP3.
6U/D
Increment/decrement for up/down interface.
7V
CC
System supply voltage
8R
L0
Low terminal of DCP0.
9R
H0
High terminal of DCP0.
10 R
W0
Wiper terminal of DCP0.
12 WP
Hardware write protect
13 SDA Serial data input/output for 2-wire bus.
15 R
L1
Low terminal of DCP1.
16 R
H1
High terminal of DCP1.
17 R
W1
Wiper terminal DCP1.
18 V
SS
System ground
X9252
3
FN8167.3
July 24, 2014
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Pin Descriptions
Bus Interface Pins
Serial Data Input/Output (SDA)
The SDA is a bidirectional serial data input/output pin for the
2-wire interface. It receives device address, operation code,
wiper register address and data from a 2-wire external master
device at the rising edge of the serial clock SCL, and it shifts
out data after each falling edge of the serial clock SCL.
SDA requires an external pull-up resistor, since it’s an open
drain output.
Serial Clock (SCL)
This input is the serial clock of the 2-wire and Up/Down
interface.
Device Address (A0, A1, A2)
The Address inputs are used to set the least significant 3 bits of
the 8-bit 2-wire interface slave address. A match in the slave
address serial data stream must be made with the Address
input pins in order to initiate communication with the X9252. A
maximum of 8 devices may occupy the 2-wire serial bus.
Chip Select (CS
)
When the CS
pin is low, increment or decrement operations
are possible using the SCL and U/D
pins. The 2-wire
interface is disabled at this time. When CS
is high, the 2-wire
interface is enabled.
Up or Down Control (U/D
)
The U/D
input pin is held HIGH during increment operations
and held LOW during decrement operations.
DCP Select (DS1 and DS0)
The DS1 and DS0 select one of the four DCPs for an
Up/Down interface operation.
Hardware Write Protect Input (WP
)
When the WP
pin is set low, “write” operations to nonvolatile
DCP Data Registers are disabled. This includes both 2-wire
interface nonvolatile “Write”, and Up/Down interface “Store”
operations.
DCP Pins
R
H0
, R
L0
, R
H1
, R
L1
, R
H2
, R
L2
, R
H3
, and R
L3
These pins are equivalent to the terminal connections on
mechanical potentiometers. Since there are 4 DCPs, there is
one set of R
H
and R
L
for each DCP.
R
W0
, R
W1
, R
W2
, and R
W3
The wiper pins are equivalent to the wiper terminal of
mechanical potentiometers. Since there are four DCPs,
there are 4 R
W
pins.
19 CS Chip select for Up/Down interface.
20 R
W2
Wiper terminal of DCP2.
21 R
H2
High terminal of DCP2.
22 R
L2
Low terminal of DCP2.
23 SCL Serial clock for 2-wire bus.
Pin Descriptions (Continued)
PIN # SYMBOL DESCRIPTION
X9252
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X9252YV24IZ-2.7

Mfr. #:
Buy X9252YV24IZ-2.7
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs 256-TAP2 8KOHM 2 7-5 5V DCP-24 INDUSTRIAL
Lifecycle:
New from this manufacturer.
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