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X9252YV24IZ-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
7
FN8167.3
July 24, 2014
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Increment/Decrement Timing
NOTES:
3. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
W(n)(actual)
)-V(R
W(n)(expected)
)]/MI
V(R
W(n)(expected)
) = n(V(R
H
)-V(R
L
))/255 + V(R
L
), with n from 0 to 255.
4. Relative linearity is a measure of the error in step size between taps = [V(R
W(n+1)
)-(V(R
W(n)
) + MI)]/MI, with n from 0 to 254
5. 1 Ml = Minimum Increment = [V(R
H
)-V(R
L
)]/255.
6. Typical values are for T
A
= +25°C and nominal supply voltage.
7. This parameter is not 100% tested.
8. Ratiometric temperature coefficient = (V(R
W
)
T1(n)
-V(R
W
)
T2(n)
)/[V(R
W
)
T1(n)
(T1-T2)] x 10
6
, with T1 and T2 being 2 temperatures, and n from 0
to 255.
9. Measured with wiper at tap position 255, R
L
grounded, using test circuit.
10. t
WC
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time from a valid
STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS
of a valid “Store” operation of
the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle.
11. The recommended power up sequence is to apply V
CC
/V
SS
first, then the potentiometer voltages. During power-up, the data sheet parameters
for the DCP do not fully apply until t
D
after V
CC
reaches its final value. In order to prevent unwanted tap position changes, or an inadvertant
store, bring the CS
pin high before or concurrently with the V
CC
pin on power-up.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
High-Voltage Write Cycle Timing
SYMBOL PARAMETER TYP MAX UNITS
t
WC
(Notes 7, 10)
Non-Volatile Write Cycle Time 5 10 ms
XDCP Timing
SYMBOL PARAMETER MIN MAX UNITS
t
WRL
(Note 7) SCL Rising Edge To Wiper Code Changed, Wiper Response Time After Instruction
Issued (All Load Instructions)
520µs
X9252
8
FN8167.3
July 24, 2014
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Test Circuit Equivalent Circuit
Principles of Operation
The X9252 is an integrated circuit incorporating four resistor
arrays, their associated registers and counters, and the
serial interface logic providing direct communication
between the host and the digitally controlled potentiometers.
This section provides detail description of the following:
-Resistor Array
- Up/Down Interface
- 2-wire Interface
Resistor Array Description
The X9252 is comprised of four resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
Hi
and
R
Li
inputs) (see Figure 1).
At both ends of each array and between each resistor
segment is a switch connected to the wiper (R
Wi
) pin.
Within each individual array only one switch may be turned
on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 8 bits of the WCR (WCR[7:0]) are decoded to
select and enable one of 256 switches (see Table 1
). Note
that each wiper has a dedicated WCR. When all bits of a
WCR are zeroes, the switch closest to the corresponding R
L
pin is selected. When all bits of a WCR are ones, the switch
closest to the corresponding R
H
pin is selected.
The WCR is volatile and may be written directly. There are
four non-volatile Data Registers (DR) associated with each
WCR. Each DR can be loaded into WCR. All DRs and
WCRs can be read or written.
Power-Up and Down Requirements
During power-up, CS must be high, to avoid inadvertant
“store” operations. At power-up, the contents of Data
Registers DR00, DR10, DR20, and DR30, are loaded into
the corresponding wiper counter register.
FORCE
CURRENT
TEST POINT
R
W
C
H
C
L
R
W
R
TOTAL
C
W
R
H
R
L
ONE
WCR[7:0]
R
Hi
R
Wi
R
Li
= FF hex
255
254
253
252
OF
256
DECODER
VOLATILE
8-BIT
WIPER
COUNTER
REGISTER
WCRi
FOUR
NON-VOLATILE
DATA
REGISTERS
DRi0, DRi1,
DRi2, and
DRi3
i = 0, 1, 2, AND 3
INTERFACE CONTROL AND
WCR[7:0]
= 00 hex
2
1
0
VOLATILE STATUS REGISTER (SR)
(SHARED BY THE FOUR DCPs)
WP
SCL
SDA
A2, A1, A0
CS
U/D
DS1, DS0
FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP
X9252
9
FN8167.3
July 24, 2014
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Up/Down Interface Operation
The SCL, U/D, CS, DS0 and DS1 inputs control the
movement of the wiper along the resistor array. With CS
set
LOW the device is selected and enabled to respond to the
U/D
and SCL inputs. HIGH-to-LOW transitions on SCL will
increment or decrement (depending on the state of the U/D
input) a wiper counter register selected by DS0 and DS1.
The output of this counter is decoded to select one of 256
wiper positions along the resistor array.
The value of the counter is stored in nonvolatile Data
Registers DRi0 whenever CS
transitions HIGH while the
SCL and WP
inputs are HIGH. “i” indicates the DCP number
selected with pins DS1 and DS0. During a “Store” operation
bits DRSel1 and DRSel0 in the Status Register must be both
“0”, which is their power up default value. Other
combinations are reserved and must not be used.
The system may select the X9252, move the wiper, and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep SCL LOW while taking CS
HIGH. The new wiper position will be maintained until
changed by the system or until a power-down/up cycle
recalled the previously stored data.
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The state of U/D
may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
The 2-wire interface is disabled while CS
remains LOW.
Mode Selection for Up/Down Control
2-Wire Serial Interface
Protocol Overview
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. The X9252
operates as a slave in all applications.
All 2-wire interface operations must begin with a START,
followed by a Slave Address byte. The Slave Address
selects the X9252, and specifies if a Read or Write operation
is to be performed.
All Communication over the 2-wire interface is conducted by
sending the MSB of each byte of data first.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. The SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions
(see Figure 2
). On power-up of the X9252, the SDA pin is in
the input mode.
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met (see Figure 2
).
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW-to-HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read sequence.
A STOP condition can only be issued after the transmitting
device has released the bus (see Figure 2
).
TABLE 1. DCP SELECTION FOR UP/DOWN CONTROL
DS1 DS0 SELECTED DCP
00 DCP0
01 DCP1
10 DCP2
11 DCP3
CS SCL U/D MODE
L H Wiper Up
L L Wiper Down
H X Store Wiper Position to nonvolatile
memory if WP
pin is high. No store,
return to standby, if WP
pin is low.
H X X Standby
L X No Store, Return to Standby
L H Wiper Up (not recommended)
L L Wiper Down (not recommended)
X9252
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X9252YV24IZ-2.7

Mfr. #:
Buy X9252YV24IZ-2.7
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs 256-TAP2 8KOHM 2 7-5 5V DCP-24 INDUSTRIAL
Lifecycle:
New from this manufacturer.
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