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X9252YV24IZ-2.7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
13
FN8167.3
July 24, 2014
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DCP Addressing for 2-Wire Interface
Once the register number has been selected by a 2-wire
instruction, then the DCP number is determined by the
Address Byte of the following instruction. Note again that this
enables a complete page write of the DRs of all four
potentiometers at once. The register addresses accessible
in the X9252 include:
All other address bits in the Address Byte must be set to “0”
during 2-wire write operations and their value should be
ignored when read.
Byte Write Operation
For any Byte Write operation, the X9252 requires the Slave
Address byte, an Address Byte, and a Data Byte
(see Figure 7
). After each of them, the X9252 responds with
an ACK. The master then terminates the transfer by
generating a STOP condition. At this time, if the write
operation is to a volatile register (WCR, or SR), the X9252 is
ready for the next read or write operation. If the write
operation is to a nonvolatile register (DR), and the WP
pin is
high, the X9252 begins the internal write cycle to the
nonvolatile memory. During the internal nonvolatile write
cycle, the X9252 does not respond to any requests from the
master. The SDA output is at high impedance.
The SR bits and WP
pin determine the register being
accessed through the 2-wire interface (see Table 2
).
As noted before, any write operation to a Data Register
(DR), also transfers the contents of all the data registers in
that row to their corresponding WCR.
For example, to write 3Ahex to the Data Register 1 of DCP2
the following sequence is required:
During the sequence of this example, WP
pin must be high,
and A0, A1, and A2 pins must be low. When completed, the
DR21 register and the WCR2 will be set to 3Ah and the other
Data Register in Row 1 will transfer their other contents to
the respective WCR’s
TABLE 3. 2-WIRE INTERFACE ADDRESS BYTE
ADDRESS (HEX) CONTENTS
0 DCP 0
1 DCP 1
2 DCP 2
3 DCP 3
4 Not Used
5 Not Used
6 Not Used
7 Status Register
START
Slave Address 0101 0000
ACK
Address Byte 0000 0111
ACK
Data Byte 0000 0011
ACK
Note: at this ACK, the WCRs are all updated with their respective DR.
STOP
START
Slave Address 0101 0000
ACK
Address Byte 0000 0010
ACK
Data Byte 0011 1010
ACK
STOP
(Hardware Address = 000,
and a Write Command)
(Indicates Status Register
Address)
(Data Register 1 and
NVEnable Selected)
(Hardware Address = 000,
(Access DCP2)
(Write Data Byte 3Ah)
Write Command)
FIGURE 7. BYTE WRITE SEQUENCE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
A
C
K
0
0
011
A
C
K
WRITE
SIGNAL AT SDA
X9252
14
FN8167.3
July 24, 2014
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Page Write Operation
As stated previously, the memory is organized as a single
Status Register (SR), and four pages of four registers each.
Each page contains one Data Register for each DCP. The
order of the bytes within a page is DR0i, followed by DR1i,
followed by DR2i, and then DR3i, with i being the Data
Register number (0, 1, 2, or 3). Normally a page write
operation will be used to efficiently update all four data
registers and WCR in a single write command, starting at
DCP0 and finishing with DCP3.
In order to perform a Page Write operation to the memory
array, the NVEnable bit in the SR must first be set to “1”.
A Page Write operation is initiated in the same manner as
the byte write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 4 bytes (see Figure 8
). After the receipt of
each byte, the X9252 responds with an ACK, and the
internal DCP address counter is incremented by one. The
page address remains constant. When the counter reaches
the end of the page (DR3i, 03hex), it “rolls over” and goes
back to the first byte of the same page (DR0i, 00hex).
For example, if the master writes 3 bytes to a page starting
at location DR22, the first 2 bytes are written to locations
DR22 and DR32, while the last byte is written to locations
DR02. Afterwards, the DCP counter would point to location
DR12. If the master supplies more than 4 bytes of data, then
new data overwrites the previous data, one byte at a time.
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle. If the WP
pin is low,
the nonvolatile write cycle doesn’t start and the bytes are
discarded.
Notice that the Data Bytes are also written to the WCR of the
corresponding DCPs, therefore in the above example,
WCR2, WCR3, and WCR0 are also written and WCR1 is
updated with the contents of DR12.
2 < n < 4
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
A
C
K
A
C
K
0
0
011
DATA BYTE (1)
S
T
O
P
A
C
K
A
C
K
DATA BYTE (n)
WRITE
FIGURE 8. PAGE WRITE OPERATION
X9252
15
FN8167.3
July 24, 2014
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Move/Read Operation
The Move/Read operation simultaneously reads the
contents of a Data Register (DR) and moves the contents
into the corresponding DCP’s WCR and the WCRs of all
DCPs are updated with the content of their corresponding
DR. Move/Read operation consists of a one byte, or three
byte instruction followed by one or more Data Bytes
(see Figure 9
). To read an arbitrary byte, the master initiates
the operation issuing the following sequence: a START, the
Slave Address byte with the R/W
bit set to “0”, an Address
Byte, a second START, and a second Slave Address byte
with the R/W
bit set to “1”. After each of the three bytes, the
X9252 responds with an ACK. Then the X9252 transmits
Data Bytes as long as the master responds with an ACK
during the SCL cycle following the eight bit of each byte. The
master terminates the Move/Read operation (issuing a
STOP condition) following the last bit of the last Data Byte.
The first byte being read is determined by the current DCP
address and by the Status Register bits, according to Table
2. If more than one byte is read, the DCP address is
incremented by one after each byte, in the same way as
during a Page Write operation. After reaching DCP3, the
DCP address “rolls over” to DCP0.
On power-up, the Address pointer is set to the Data Register
0 of DCP0.
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
SLAVE
ADDRESS WITH
R/W
= 0
ADDRESS
BYTE
A
C
K
A
C
K
0
0
011
S
T
O
P
A
C
K
0
1
011
SLAVE
ADDRESS WITH
R/W
= 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
ONE OR MORE DATA BYTES
CURRENT ADDRESS READSETTING THE CURRENT ADDRESS
RANDOM ADDRESS READ
FIGURE 9. MOVE/READ SEQUENCE
X9252
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

X9252YV24IZ-2.7

Mfr. #:
Buy X9252YV24IZ-2.7
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs 256-TAP2 8KOHM 2 7-5 5V DCP-24 INDUSTRIAL
Lifecycle:
New from this manufacturer.
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