CS5361
10 DS467F2
DC ELECTRICAL CHARACTERISTICS
GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode.
Notes: 8. Power Down Mode is defined as RST = Low with all clocks and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
THERMAL CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Power Supply Current VA = 5 V
(Normal Operation) VL,VD = 5 V
VL,VD = 3.3 V
I
A
I
D
I
D
-
-
-
17.5
22
14.5
21.5
27.5
17
mA
mA
mA
Power Supply Current VA = 5 V
(Power-Down Mode) (Note 8) VL,VD = 5 V
I
A
I
D
-
-
100
100
-
-
µA
µA
Power Consumption
(Normal Operation) VA, VD, VL = 5 V
VA = 5 V, VL, VD = 3.3 V
(Power-Down Mode)
-
-
-
-
-
-
198
135
1
243
161
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 9) PSRR - 65 - dB
V
Q
Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
2.5
25
0.01
-
-
-
V
k
mA
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
5
15
0.01
-
-
-
V
k
mA
Parameter Symbol Min Typ Max Units
High-Level Input Voltage (% of VL) V
IH
70% - - V
Low-Level Input Voltage (% of VL) V
IL
--30%V
High-Level Output Voltage at I
o
= 100 µA(% of VL)V
OH
70% - - V
Low-Level Output Voltage at I
o
= 100 µA(% of VL)V
OL
--15%V
OVFL
Current Sink
I
ovfl
--4.0mA
Input Leakage Current (all pins except SCLK and LRCK) I
in
-10 - 10 µA
Input Leakage Current (SCLK and LRCK) I
in
-25 - 25 µA
Parameter Symbol Min Typ Max Unit
Allowable Junction Temperature - - 135 °C
Junction to Ambient Thermal Impedance
(Multi-layer PCB) TSSOP
(Multi-layer PCB) SOIC
(Single-layer PCB) TSSOP
(Single-layer PCB) SOIC
θ
JA-TM
θ
JA-SM
θ
JA-TS
θ
JA-SS
-
-
-
-
70
60
105
80
-
-
-
-
°C/W
°C/W
°C/W
°C/W
CS5361
DS467F2 11
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic “0” = GND = 0 V; Logic “1” = VL, C
L
= 20 pF
Parameter Symbol Min Typ Max Unit
Output Sample Rate Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
2
50
100
-
-
-
51
102
204
kHz
kHz
kHz
OVFL
to LRCK edge setup time
t
setup
16/f
sclk
--s
OVFL
to LRCK edge hold time
t
hold
1/f
sclk
--s
OVFL
time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz
Fs = 48, 96, 192 kHz
-
-
740
680
-
-
ms
ms
MCLK Specifications
MCLK Period t
clkw
38 - 1953 ns
MCLK Pulse Duty Cycle 40 50 60 %
Master Mode
SCLK falling to LRCK t
mslr
-20 - 20 ns
SCLK falling to SDOUT valid t
sdo
0 - 32 ns
SCLK Duty Cycle - 50 - %
Slave Mode
Single Speed
Output Sample Rate Fs 2 - 51 kHz
LRCK Duty Cycle 40 50 60 %
SCLK Period t
sclkw
153 - - ns
SCLK Duty Cycle 45 50 55 %
SCLK falling to SDOUT valid t
dss
- - 32 ns
SCLK falling to LRCK edge t
slrd
-20 - 20 ns
Double Speed
Output Sample Rate Fs 50 - 102 kHz
LRCK Duty Cycle 40 50 60 %
SCLK Period t
sclkw
153 - - ns
SCLK Duty Cycle 45 50 55 %
SCLK falling to SDOUT valid t
dss
- - 32 ns
SCLK falling to LRCK edge t
slrd
-20 - 20 ns
Quad Speed
Output Sample Rate Fs 100 - 204 kHz
LRCK Duty Cycle 40 50 60 %
SCLK Period t
sclkw
77 - - ns
SCLK Duty Cycle 45 50 55 %
SCLK falling to SDOUT valid t
dss
- - 32 ns
SCLK falling to LRCK edge t
slrd
-8 - 3 ns
CS5361
12 DS467F2
Figure 13. Master Mode, Left Justified SAI Figure 14. Slave Mode, Left Justified SAI
SCLK output
t
msl r
SDOUT
t
sdo
LRCK
output
MSB MSB-1
CLK input
LRCK input
dss
t
MSB MSB-1 MSB-2
t
sclkw
SDOUT
srdl
t
Figure 15. Master Mode, I
2
S SAI Figure 16. Slave Mode, I
2
S SAI
SCLK input
LRCK input
MSB
MSB-1
t
sclkw
SDOUT
srdl
t
dss
t
SCLK input
LRCK input
MSB
MSB-1
t
sclkw
SDOUT
srdl
t
dss
t
OVFL
t
setup
LRCK
t
hold
Figure 17. OVFL Output Timing

CS5361-KZZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Audio A/D Converter ICs 24-Bit 114dB 192kHz Multi-Bit ADC
Lifecycle:
New from this manufacturer.
Delivery:
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