IDT821054APF8 Datasheet IDT821054APF, IDT821054APFG, IDT821054APF8 | P13-P15

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE

specified channel. When one bit of IE[4:0] is ‘0’, the corresponding

interrupt is ignored (disabled), otherwise, the corresponding interrupt is

recognized (enabled).

Multiple interrupt sources can be enabled at the same time. All

interrupts can be cleared simultaneously by executing a write operation

to global register GREG2. Additionally, the interrupts caused by all four

channels’ SI1 and SI2 status changes can be cleared by applying a read

operation to GREG9. If SB1, SB2 and SB3 pins are configured as

inputs, a read operation to GREG10, GREG11 and GREG12 clears the

interrupt generated by the corresponding SB port of all four channels. A

read operation to LREG4 clears all 7 interrupt sources of the specified

channel.

2.6 DEBOUNCE FILTERS

For each channel, the IDT821054A provides two debounce filter

circuits: Debounced Switch Hook (DSH) Filter for the SI1 signal and

Ground Key (GK) Filter for the SI2 signal. See Figure - 5 for details. The

two debounce filters are used to buffer the input signals on SI1 and SI2

pins before changing the state of the SLIC Debounced Input SI1/SI2

DSH and GK filters.

The DSH[3:0] bits in LREG3 are used to program the debounce

period of the SI1 input of the corresponding channel. The DSH filter is

initially clocked at half of the frame sync rate (250

µs). Any data

changing at this sample rate resets a counter that clocks at the rate of 2

ms. The value of the counter is programmable from 0 to 30 via LREG3.

The debounced SI1 signals of Channel 4 to 1 are written to the SIA[3:0]

bits in GREG9. The corresponding SIA bit will not be updated until the

value of the counter is reached. The SI1 pin usually contains the SLIC

switch hook status.

The GK[3:0] bits in LREG3 are used to program the debounce

interval of the SI2 input of the corresponding channel. The debounced

SI2 signals of Channel 4 to 1 are written to the SIB[3:0] bits in GREG9.

The GK debounce filter consists of a six-state up/down counter that

ranges between 0 and 6. This counter is clocked by the GK timer at the

sampling period of 0-30 ms, which is programmed via LREG3. If the

sampled value is low, the value of the counter will be decremented by

each clock pulse. If the sampled value is high, the value of the counter is

incremented by each clock pulse. When the value increases to 6, it sets

a latch whose output is routed to the corresponding SIB bit. If the value

decreases to 0, the latch will be cleared and the output bit will be set to

0. In other cases, the latch and the SIB status remain in their previous

state without being changed. In this way, at least six consecutive GK

clocks with the debounce input remaining at the same state can effect

an output change.

Figure - 5 Debounce Filter

2.7 CHOPPER CLOCK

The IDT821054A provides two programmable chopper clock outputs

CHCLK1 and CHCLK2. They can be used to drive the power supply

switching regulators on SLICs. The two chopper clocks are synchronous

to MCLK. The CHCLK1 outputs a signal which clock cycle is

programmable from 2 to 28 ms. The CHCLK2 outputs a signal which

frequency can be 256 kHz, 512 kHz or 16.384 MHz. The frequencies of

the two chopper clocks are programmed by global register GREG5.

2.8 DUAL TONE AND RING GENERATION

The IDT821054A provides two tone generators (tone generator 0

and tone generator 1) for each channel. They can produce signals such

as test tone, DTMF, dial tone, busy tone, congestion tone and Caller-ID

Alerting Tone, and output it to the VOUT pin.

The dual tone generators of each channel can be enabled by setting

the TEN0 and TEN1 bits in LREG10 to ‘1’respectively.

The frequency and amplitude of the tone signal are programmed by

the Coe-RAM. The frequency and amplitude coefficients are calculated

by the following formulas:

Frequency coefficient = 32767∗ cos(f / 8000 ∗ 2 ∗ π)

Amplitude coefficient = A ∗ 32767 ∗ sin(f / 8000 ∗ 2 ∗ π)

Herein, 'f' is the desired frequency of the tone signal, 'A' is the scaling

parameter of the amplitude. The range of 'A' is from 0 to 1.

A = 1, corresponds to the maximum amplitude of 1.57 V.

DQ DQ DQ DQ

DSH[3:0]

Debounce

Period

(0-30 ms)

GK[3:0]

Debounce

Interval

(0-30 ms)

up/

down

6 states

Up/down

Counter

7 bit Debounce

Counter

7 bit Debounce

Counter

= 0

≠ 0

SIB

SIA

SI1

4 kHz

SI2

RST

FS/2

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE

A = 0, corresponds to the minimum amplitude of 0 V.

It is a linear relationship between 'A' and the amplitude. That is, if

A=β ( 0<β<1), the amplitude will be 1.57 ∗ β (V).

The frequency range is from 25 Hz to 3400 Hz. The frequency

tolerances are as the following:

25 Hz < f < 40 Hz, tolerance < ±12%

40 Hz < f < 60 Hz, tolerance < ±5%

60 Hz < f < 100 Hz, tolerance < ±2.5%

100 Hz < f < 3400 Hz, tolerance < ±1%

The frequency and amplitude coefficients should be converted to

corresponding hexadecimal values before being written to the Coe-

RAM. Refer to “9 Appendix: IDT821054A Coe-RAM Mapping” for the

address of the tone coefficients.

The ring signal is a special signal generated by the dual tone

generators. When only one tone generator is enabled, or dual tone

generators produce the same tone signal and frequency of the tone

meets the ring signal requirement (10 Hz to 100 Hz), a ring signal will be

generated and output to the VOUT pin.

2.9 LEVEL METERING

The IDT821054A integrates a level meter which is shared by all 4

channels. The level meter is designed to emulate the off-chip PCM test

equipment so as to facilitate the line-card, subscriber line and users

telephone set monitoring. The level meter tests the return signal and

reports the measurement result via the MPI interface. When combined

with tone generation and loopbacks, it allows the microprocessor to test

the channel integrity. The signal on the channel selected by the CS[1:0]

bits in GREG21 will be metered.

The level meter is enabled by setting the LMO bit in GREG21 to ‘1’. A

level meter counter register (GREG20) is used to set the value of time

cycles for sampling the PCM data (8 kHz sampling rate). The output of

level meter is sent to the level meter result registers GREG18 and

GREG19. The LVLL[7:0] bits in GREG18 contain the lower 7 bits of the

result and a data-ready bit (LVLL[0]), while the LVLH[7:0] bits in

GREG19 contain the higher 8 bits of the result. An internal accumulator

sums the rectified samples until the value set in GREG20 is reached. By

then, the LVLL[0] bit is set to ‘1’ and accumulation result is latched into

GREG18 and GREG19 simultaneously.

Once the higher byte of result (GREG19) is read, the LVLL[0] bit in

GREG18 will be reset. It will be set to ‘1’ again by a new data available.

The contents of GREG18 and GREG19 will be overwritten by the

following metering result if they have not been read out yet. To read the

level meter result registers, it is recommended to read GREG18 (lower

byte of result) first.

The L/C bit in GREG21 determines the level meter operation mode. If

the L/C bit is ‘1’, it means that metering mode is selected. In this mode,

the linear PCM data will be sent to the level meter and the metering

result will be output to GREG18 and GREG19. With this result, the

signal level can be calculated.

For A-law compressed PCM code or linear PCM code, the signal

level can be calculated by the following formula:

For

µ-law compressed PCM code, the signal level can be calculated

by the following formula:

Result

: the value in the level meter result registers (GREG18

& GREG19);

Countnumber

:the count number of the level meter (set in GREG20).

If the L/C bit is ‘0’, it means that message mode is selected. In this

mode, the compressed PCM data will be output to GREG19

transparently without metering.

Refer to the Application Note for further details on the level meter.

2.10 CHANNEL POWER DOWN/STANDBY MODE

Each individual channel of the IDT821054A can be powered down

independently by setting the PD bit in LREG9 to ‘1’. If one channel is

powered down and enters the standby mode, the PCM data transfer and

the D/A, A/D converters of this channel will be disabled. In this way, the

power consumption of the device can be reduced.

When the IDT821054A is powered up or reset, all four channels will

be powered down. All circuits that contain programmed information

retain their data after power down. The microprocessor interface is

always active so that new commands can be received and executed.

2.11 POWER DOWN/SUSPEND MODE

A suspend mode is provided for the whole chip to save power. The

suspend mode saves much more power consumption than the standby

mode. In this mode, the PLL block is turned off and the DSP operation is

disabled. Only global and local commands can be executed, the RAM

operation is disabled as the internal clock has been turned off. The PLL

block is powered down by setting the PPD bit in GREG22 to ‘1’. Once

the PLL and all four channels are powered down, the IDT821054A will

enter the suspend mode.

A dbm0

()20

Result

π××

Countnumber

28192××

--------------------------------------------------------------







log× 3.14+=

A dbm0

()20

Result

π××

Countnumber

28192××

--------------------------------------------------------------







log× 3.17+=

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE

3 OPERATING THE IDT821054A

3.1 PROGRAMMING DESCRIPTION

The IDT821054A is programmed by writing commands to registers

and coefficient RAM. A Channel Program Enable register (GREG6) is

provided for addressing individual or multiple channels. The CE[3:0] bits

in this register are assigned to Channel 4 to Channel 1 respectively. The

channels are enabled to be programmed by setting their respective CE

bits to ‘1’. If two or more channels are enabled, the successive write

commands will be effective to all enabled channels. A broadcast mode

can be implemented by simply enabling all four channels before

performing other write-operation. The broadcast mode is very useful for

configuring the coefficient RAM of the IDT821054A in a large system.

But for read operations, multiple addressing is not allowed.

The IDT821054A uses an Identification Code to distinguish itself

from other devices in the system. When being read, the IDT821054A will

output an Identification Code of 81H first to indicate that the following

data bytes are from the IDT821054A.

3.1.1 COMMAND TYPE AND FORMAT

The IDT821054A provides three types of commands as follows:

Local Command (LC), which is used to address the local registers of

the specified channel(s).

Global Command (GC), which is used to address the global registers

of all four channels.

RAM Command (RC), which is used to address the coefficient RAM

(Coe-RAM).

The format of the command is as the following:

R/W: Read/Write Command bit

b7 = 0: Read Command

b7 = 1: Write Command

CT: Command Type

b6 b5 = 00: LC - Local Command

b6 b5 = 01: GC - Global Command

b6 b5 = 10: Not Allowed

b6 b5 = 11: RC - RAM Command

Address: b[4:0], specify one or more local/global registers or a block

of Coe-RAM to be addressed.

For Local Command and Global Command, the b[4:0] bits are used

to specify the address of the local registers and global registers

respectively.

For RAM Command, b[4:0] bits are used to specify the block of the

Coe-RAM.

3.1.2 ADDRESSING THE LOCAL REGISTERS

When addressing the local registers, users must specify which

channel(s) will be addressed first. If two or more channels are specified

via GREG6, the corresponding local registers of the specified channels

will be addressed by a Local Command at the same time.

The IDT821054A provides a consecutive adjacent addressing

method for accessing the local registers. According to the address

specified in a Local Command, there will be 1 to 4 adjacent local

registers to be addressed automatically, with the highest order first. For

example, if the address specified in a Local Command ends with ‘11’

(b1b0 = 11), 4 adjacent registers will be addressed by this command; if

b1b0 = 10, 3 adjacent registers will be addressed. See Table - 1 for

details.

When addressing local registers, the procedure of consecutive

adjacent addressing can be stopped by the CS signal at any time. If CS

is changed from low to high, the operation to the current register and the

next adjacent registers will be aborted. However, the previous operation

results will not be affected.

3.1.3 ADDRESSING THE GLOBAL REGISTERS

For global registers are shared by all four channels, it is no need to

specify the channel(s) before addressing a global register. Except for

this, the global registers are addressed in a similar way as local

registers. The procedure of consecutive adjacent addressing can be

stopped by the CS signal at any time.

3.1.4 ADDRESSING THE COE-RAM

There are totally 40 words of Coe-RAM. They are divided to 5

blocks. Each block consists of 8 words. Each word is 14-bit wide.

The 5 blocks of the Coe-RAM are assigned for different filter

coefficients as shown below (refer to “9 Appendix: IDT821054A Coe-

RAM Mapping” for the address of the Coe-RAM):

Block 1: IMF RAM (Word 0 - Word 7), containing the Impedance

Matching Filter coefficient.

Block 2: ECF RAM (Word 8 - Word 15), containing the Echo

Cancellation Filter coefficient.

Block 3: GIS RAM (Word 16 - Word 19) and Tone Generator RAM

(Word 20 - Word 23), containing the Gain of Impedance Scaling and

dual tone coefficients.

Block 4: FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31),

containing the coefficient of the Frequency Response Correction in

Transmit Path and the Gain in Transmit Path;

Block 5: FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39),

containing the coefficient of the Frequency Response Correction in

Receive Path and the Gain in Receive Path.

The Coe-RAM blocks used for containing the IMF, ECF, GIS, FRX,

GTX, FRR and GRX coefficients are shared by all four channels. When

coefficients are written to these blocks, they will be used by all four

channels. But the four words (word 20 to 23), which contain the dual

b7 b6 b5 b4 b3 b2 b1 b0

R/W CT Address

Table - 1 Consecutive Adjacent Addressing

Address Specified in a Local

Command

In/Out Data

Bytes

Address of the Local

Registers to be accessed

b[4:0] = XXX11

(b1b0 = 11, four bytes of data)

byte 1 XXX11

byte 2 XXX10

byte 3 XXX01

byte 4 XXX00

b[4:0] = XXX10

(b1b0 = 10, three bytes of data)

byte 1 XXX10

byte 2 XXX01

byte 3 XXX00

b[4:0] = XXX01

(b1b0 = 01, two bytes of data)

byte 1 XXX01

byte 2 XXX00

b[4:0] = XXX00

(b1b0 = 00, one byte of data)

byte 1 XXX00

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

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