39
IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
8.3 PCM INTERFACE TIMING
Figure - 9 Transmit and Receive Timing
Figure - 10 Typical Frame Sync Timing (2 MHz Operation)
Symbol Description Min. Typ. Max. Units Test Conditions
t21 Data enable delay time 5 70 ns
t22 Data delay time from BCLK 5 70 ns
t23 Data float delay time 5 70 ns
t24 Frame sync setup time 25 t4 − 50 ns
t25 Frame sync hold time 50 ns
t26 TSX1 or TSX2 enable delay time 5 80 ns
t27 TSX1 or TSX2 disable delay time 5 80 ns
t28 Receive data setup time 25 ns
t29 Receive data hold time 5 ns
123456781
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BCLK
FS
DX1/
DX2
DR1/
DR2
t25
t24
Time Slot
t23
t22
t21
t28
t29
TSX1 /
TSX2
t26
t27
Note: This timing diagram only applies to the situation of receiving data on falling edges and transmitting data on rising edges.
2728293031012345678910111213141516 17 18 19 20 21 22 23 24 25 26
X0 X1 X2 X3
R0 R1 R2 R3
Time Slot
FS
DX1/DX2
DR1/DR2
TSX1 / TSX2
