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IDT821054APF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
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IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
For the global and local registers described below, it should be noted that:
1. R/W = 0, Read command. R/W = 1, Write command.
2. The reserved bit(s) in the registers must be filled in ‘0’ in write operation and be ignored in read operation.
3.4.2 GLOBAL REGISTERS LIST
GREG1: No Operation, Write (A0H); Version Number, Read (20H)
By applying a read operation (20H) to this register, users can read out the version number of the IDT821054A. The default value is 01H.
To write to this register (no operation), a data byte of FFH must follow the write command (A0H) to ensure proper operation.
GREG2: Interrupt Clear, Write Only (A1H)
All interrupts on SLIC I/O will be cleared by applying a write operation to this register. Note that a data byte of FFH must follow the write
command (A1H) to ensure proper operation.
GREG3: Software Reset, Write Only (A2H)
A write operation to this register resets all local registers, but does not reset global registers and the Coe-RAM. Note that when writing to
this register, a data byte of FFH must follow the write command (A2H) to ensure proper operation.
GREG4: Hardware Reset, Write Only (A3)
A write operation to this register is equivalent to setting the RESET pin to logic low (Refer to “3.3 Default State After Reset” on page 19
for details). Note that when applying this write command, a data byte of FFH must follow to ensure proper operation.
GREG5: Chopper Clock Selection, Read/Write (24H/A4H)
This register is used to select the frequency of the CHclk2 and CHclk1 output signals.
CHclk2[1:0] = 00: the output of chclk2 is set to high permanently (default);
CHclk2[1:0] = 01: chclk2 outputs a digital signal with the frequency of 512 kHz;
CHclk2[1:0] = 10: chclk2 outputs a digital signal with the frequency of 256 kHz;
CHclk2[1:0] = 11: chclk2 outputs a digital signal with the frequency of 16384 kHz;
CHclk1[3:0] = 0000: the output of chclk1 is set to high permanently (default);
CHclk1[3:0] = 0001: chclk1 outputs a digital signal with the frequency of 1000/2 Hz;
CHclk1[3:0] = 0010: chclk1 outputs a digital signal with the frequency of 1000/4 Hz;
CHclk1[3:0] = 0011: chclk1 outputs a digital signal with the frequency of 1000/6 Hz;
CHclk1[3:0] = 0100: chclk1 outputs a digital signal with the frequency of 1000/8 Hz;
CHclk1[3:0] = 0101: chclk1 outputs a digital signal with the frequency of 1000/10 Hz;
CHclk1[3:0] = 0110: chclk1 outputs a digital signal with the frequency of 1000/12 Hz;
CHclk1[3:0] = 0111: chclk1 outputs a digital signal with the frequency of 1000/14 Hz;
CHclk1[3:0] = 1000: chclk1 outputs a digital signal with the frequency of 1000/16 Hz;
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0100000
b7 b6 b5 b4 b3 b2 b1 b0
Command10100001
b7 b6 b5 b4 b3 b2 b1 b0
Command10100010
b7 b6 b5 b4 b3 b2 b1 b0
Command10100011
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0100100
I/O data Reserved Chclk2[1] Chclk2[0] Chclk1[3] Chclk1[2] Chclk1[1] Chclk1[0]
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IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
CHclk1[3:0] = 1001: chclk1 outputs a digital signal with the frequency of 1000/18 Hz;
CHclk1[3:0] = 1010: chclk1 outputs a digital signal with the frequency of 1000/20 Hz;
CHclk1[3:0] = 1011: chclk1 outputs a digital signal with the frequency of 1000/22 Hz;
CHclk1[3:0] = 1100: chclk1 outputs a digital signal with the frequency of 1000/24 Hz;
CHclk1[3:0] = 1101: chclk1 outputs a digital signal with the frequency of 1000/26 Hz;
CHclk1[3:0] = 1110: chclk1 outputs a digital signal with the frequency of 1000/28 Hz;
CHclk1[3:0] = 1111: the output of chclk1 is set to low permanently.
GREG6: MCLK Selection and Channel Program Enable, Read/Write (25H/A5H)
The higher 4 bits (CE[3:0]) in this register are used to specify the desired channel(s) before addressing local registers or Coe-RAM used
for tone coefficients. The CE[0] to CE[3] bits indicate the program enable state for Channel 1 to Channel 4 respectively.
CE[0] = 0: Disabled, Channel 1 can not receive programming commands (default);
CE[0] = 1: Enabled, Channel 1 can receive programming commands;
CE[1] = 0: Disabled, Channel 2 can not receive programming commands (default);
CE[1] = 1: Enabled, Channel 2 can receive programming commands;
CE[2] = 0: Disabled, Channel 3 can not receive programming commands (default);
CE[2] = 1: Enabled, Channel 3 can receive programming commands;
CE[3] = 0: Disabled, Channel 4 can not receive programming commands (default);
CE[3] = 1: Enabled, Channel 4 can receive programming commands.
The lower 4 bits (Sel[3:0]) in this register are used to select the Master Clock frequency.
Sel[3:0] = 0000: 8.192 MHz
Sel[3:0] = 0001: 4.096 MHz
Sel[3:0] = 0010: 2.048 MHz (default)
Sel[3:0] = 0110: 1.536 MHz
Sel[3:0] = 1110: 1.544 MHz
Sel[3:0] = 0101: 3.072 MHz
Sel[3:0] = 1101: 3.088 MHz
Sel[3:0] = 0100: 6.144 MHz
Sel[3:0] = 1100: 6.176 MHz
GREG7: A/
µ-law, Linear/Compressed Code, Clock Slope and Delay Time Selection, Read/Write (26H/A6H)
The A/
µ-law select bit (A-µ) selects the companding law:
A-
µ = 0: A-law is selected (default)
A-
µ = 1: µ-law is selected.
The Voice Data Select bit (VDS) defines the format of the voice data:
VDS = 0: Compressed code (default)
VDS = 1: Linear code
The Clock Slope bits (CS[2:0]) select single or double clock and clock edges of transmitting and receiving data.
CS[2] = 0: Single clock (default)
CS[2] = 1: Double clock
CS[1:0] = 00: transmits data on rising edges of BCLK, receives data on falling edges of BCLK (default).
CS[1:0] = 01: transmits data on rising edges of BCLK, receives data on rising edges of BCLK.
CS[1:0] = 10: transmits data on falling edges of BCLK, receives data on falling edges of BCLK.
CS[1:0] = 11: transmits data on falling edges of BCLK, receives data on rising edges of BCLK.
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0100101
I/O data CE[3] CE[2] CE[1] CE[0] Sel[3] Sel[2] Sel[1] Sel[0]
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0100110
I/O data A-µ VDS CS[2] CS[1] CS[0] OC[2] OC[1] OC[0]
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IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
The PCM data Offset Configuration bits (OC[2:0]) determine that the transmit and receive time slots of PCM data offset from the FS
signal by how many periods of BCLK:
OC[2:0] = 000: 0 period of BCLK (default);
OC[2:0] = 001: 1 period of BCLK;
OC[2:0] = 010: 2 periods of BCLK;
OC[2:0] = 011: 3 periods of BCLK;
OC[2:0] = 100: 4 periods of BCLK;
OC[2:0] = 101: 5 periods of BCLK;
OC[2:0] = 110: 6 periods of BCLK;
OC[2:0] = 111: 7 periods of BCLK.
GREG8: SLIC Ring Trip Setting and Control, Read/Write (27H/A7H)
The Output Polarity Indicator bit (OPI) indicates the valid polarity of output:
OPI = 0: the selected output pin changes from high to low to activate the ring (default);
OPI = 1: the selected output pin changes from low to high to activate the ring.
The Input Polarity Indicator bit (IPI) indicates the valid polarity of input:
IPI = 0: active low (default);
IPI = 1: active high.
The Input Selection bit (IS) determines which input will be selected as the off-hook indication signal source.
IS = 0: SI1 is selected (default);
IS = 1: SI2 is selected.
The Ring Trip Enable bit (RTE) enables or disables the ring trip function block:
RTE = 0: the ring trip function block is disabled (default);
RTE = 1: the ring trip function block is enabled.
The Output Selection bits (OS[2:0]) determine which output will be selected as the ring control signal source.
OS[2:0] = 000 - 010: not defined;
OS[2:0] = 011: SB1 is selected (when SB1 is configured as an output);
OS[2:0] = 100: SB2 is selected (when SB2 is configured as an output);
OS[2:0] = 101: SB3 is selected (when SB3 is configured as an output);
OS[2:0] = 110: SO1 is selected;
OS[2:0] = 111: SO2 is selected.
GREG9: SI Data, Read Only (28H)
The SIA[3:0] bits contain the debounced data (off-hook status) on the SI1 pins of Channel 4 to Channel 1 respectively.
The SIB[3:0] bits contain the debounced data (ground key status) on the SI2 pins of Channel 4 to Channel 1 respectively.
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0100111
I/O data OPI Reserved IPI IS RTE OS[2] OS[1] OS[0]
b7 b6 b5 b4 b3 b2 b1 b0
Command00101000
I/O data SIB[3] SIB[2] SIB[1] SIB[0] SIA[3] SIA[2] SIA[1] SIA[0]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

IDT821054APF8

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IC PCM CODEC QUAD MPI 64-TQFP
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