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IDT821054APF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
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IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
GREG10: SB1 Direction Control and SB1 Status/Control Data, Read/Write (29H/A9H)
The SB1 direction control bits SB1C[3:0] in this register determine the directions of the SB1 pins of Channel 4 to Channel 1 respectively.
SB1C[0] = 0: the SB1 pin of Channel 1 is configured as input (default);
SB1C[0] = 1: the SB1 pin of Channel 1 is configured as output;
SB1C[1] = 0: the SB1 pin of Channel 2 is configured as input (default);
SB1C[1] = 1: the SB1 pin of Channel 2 is configured as output;
SB1C[2] = 0: the SB1 pin of Channel 3 is configured as input (default);
SB1C[2] = 1: the SB1 pin of Channel 3 is configured as output;
SB1C[3] = 0: the SB1 pin of Channel 4 is configured as input (default);
SB1C[3] = 1: the SB1 pin of Channel 4 is configured as output.
When the SB1 pins of Channel 1 to Channel 4 are configured as inputs, the SB1[0] to SB1[3] bits contain the status of these four SB1
pins respectively. When the SB1 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB1
pins via the SB1[0] to SB1[3] bits respectively.
GREG11: SB2 Direction Control and SB2 Status/Control Data, Read/Write (2AH/AAH)
The SB2 direction control bits SB2C[3:0] in this register determine the directions of the SB2 pins of Channel 4 to Channel 1 respectively.
SB2C[0] = 0: the SB2 pin of Channel 1 is configured as input (default);
SB2C[0] = 1: the SB2 pin of Channel 1 is configured as output;
SB2C[1] = 0: the SB2 pin of Channel 2 is configured as input (default);
SB2C[1] = 1: the SB2 pin of Channel 2 is configured as output;
SB2C[2] = 0: the SB2 pin of Channel 3 is configured as input (default);
SB2C[2] = 1: the SB2 pin of Channel 3 is configured as output;
SB2C[3] = 0: the SB2 pin of Channel 4 is configured as input (default);
SB2C[3] = 1: the SB2 pin of Channel 4 is configured as output.
When the SB2 pins of Channel 1 to Channel 4 are configured as inputs, the SB2[0] to SB2[3] bits contain the status of these four SB2
pins respectively. When the SB2 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB2
pins via the SB2[0] to SB2[3] bits respectively.
GREG12: SB3 Direction Control and SB3 Status/Control Data, Read/Write (2BH/ABH)
The SB3 direction control bits SB3C[3:0] in this register determine the directions of the SB3 pins of Channel 4 to Channel 1 respectively.
SB3C[0] = 0: the SB3 pin of Channel 1 is configured as input (default);
SB3C[0] = 1: the SB3 pin of Channel 1 is configured as output;
SB3C[1] = 0: the SB3 pin of Channel 2 is configured as input (default);
SB3C[1] = 1: the SB3 pin of Channel 2 is configured as output;
SB3C[2] = 0: the SB3 pin of Channel 3 is configured as input (default);
SB3C[2] = 1: the SB3 pin of Channel 3 is configured as output;
SB3C[3] = 0: the SB3 pin of Channel 4 is configured as input (default);
SB3C[3] = 1: the SB3 pin of Channel 4 is configured as output.
When the SB3 pins of Channel 1 to Channel 4 are configured as inputs, the SB3[0] to SB3[3] bits contain the status of these four SB3
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0101001
I/O data SB1C[3] SB1C[2] SB1C[1] SB1C[0] SB1[3] SB1[2] SB1[1] SB1[0]
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0101010
I/O data SB2C[3] SB2C[2] SB2C[1] SB2C[0] SB2[3] SB2[2] SB2[1] SB2[0]
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0101011
I/O data SB3C[3] SB3C[2] SB3C[1] SB3C[0] SB3[3] SB3[2] SB3[1] SB3[0]
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IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
pins respectively. When the SB3 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB3
pins via the SB3[0] to SB3[3] bits respectively.
GREG13: Reserved for future use.
GREG14: Reserved for future use.
GREG15: Reserved for future use.
GREG16: Reserved for future use.
GREG17: Reserved for future use.
GREG18: Level Meter Result Low Byte, Read Only (31H)
This register contains the low byte of the level meter result. The default value is 00H.
The LVLL[0] bit in this register will be set to ‘1’ when the level meter result (both high and low bytes) is ready, and it will be reset to ‘0’
immediately after the high byte of result is read. To read the level meter result, it is recommended to the low byte first, then read the high
byte (LVLH[7:0] in GREG19).
GREG19: Level Meter Result High Byte, Read Only (32H)
This register contains the high byte of the level meter result. The default value is 00H.
GREG20: Level Meter Count Number, Read/Write (33H/B3H)
The CN[7:0] bits are used to set the number of time cycles for sampling the PCM data.
CN[7:0] = 0 (d): the PCM data is output to the result registers GREG18 and GREG19 directly;
CN[7:0] = N (d): the PCM data is sampled for N × 125
µs (N is from 1 to 255).
GREG21: Level Meter Channel and Linear/Compressed Mode Selection, Level Meter On/Off, Read/Write (34H/B4H)
The Level Meter On/Off bit (LMO) enables/disables the level meter.
LMO = 0: The level meter is disabled (default);
LMO = 1: The level meter is enabled.
The Linear/Compressed bit (L/C) determines the mode of level meter operation.
L/C = 0: Message mode is selected. The compressed PCM data will be output to GREG19 transparently (default).
L/C = 1: Metering mode is selected. The linear PCM data will be metered and the result will be output to the registers
GREG18 and GREG19.
b7 b6 b5 b4 b3 b2 b1 b0
Command00110001
I/O data LVLL[7] LVLL[6] LVLL[5] LVLL[4] LVLL[3] LVLL[2] LVLL[1] LVLL[0]
b7 b6 b5 b4 b3 b2 b1 b0
Command00110010
I/O data LVLH[7] LVLH[6] LVLH[5] LVLH[4] LVLH[3] LVLH[2] LVLH[1] LVLH[0]
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0110011
I/O data CN[7] CN[6] CN[5] CN[4] CN[3] CN[2] CN[1] CN[0]
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0110100
I/O data Reserved LMO L/C CS[1] CS[0]
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IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
The Level Meter Channel Select bits (CS[1:0]) select a channel, data on which will be level metered.
CS[1:0] = 00: Channel 1 is selected (default);
CS[1:0] = 01: Channel 2 is selected;
CS[1:0] = 10: Channel 3 is selected;
CS[1:0] = 11: Channel 4 is selected.
GREG22: Global Loopback Control and PLL Power Down, Read/Write (35H/B5H)
The PLL Power Down bit (PPD) controls the operation state of the PLL block.
PPD = 0: The PLL is disabled. The device is in normal operation state (default);
PPD = 1: The PLL is powered down. The device works in power-saving mode. All clocks stop running.
The Loop Control bits determine the loopback status. Refer to Figure - 4 on page 11 for detailed information.
DLB_ANA = 0: The Digital Loopback via Analog Interface is disabled (default);
DLB_ANA = 1: The Digital Loopback via Analog Interface is enabled.
ALB_8k = 0: The Analog Loopback via 8 kHz Interface is disabled (default);
ALB_8k = 1: The Analog Loopback via 8 kHz Interface is enabled.
DLB_8k = 0: The Digital Loopback via 8 kHz Interface is disabled (default);
DLB_8k = 1: The Digital Loopback via 8 kHz Interface is enabled.
DLB_DI = 0: The Digital Loopback from DR to DX is disabled (default);
DLB_DI = 1: The Digital Loopback from DR to DX is enabled.
ALB_DI = 0: The Analog Loopback from DX to DR is disabled (default);
ALB_DI = 1: The Analog Loopback from DX to DR is enabled.
b7 b6 b5 b4 b3 b2 b1 b0
Command R/W0110101
I/O data Reserved PPD DLB_ANA ALB_8k DLB_8k DLB_DI ALB_DI
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

IDT821054APF8

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IC PCM CODEC QUAD MPI 64-TQFP
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