Rev. 1.2 4/16 Copyright © 2016 by Silicon Laboratories Si53152
Si53152
PCI-E
XPRESS
G
EN
1, G
EN
2, G
EN
3,
AND
G
EN
4
F
ANOUT
B
UFFER
Features
Applications
Description
The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source
two PCIe clocks simultaneously. The device has two hardware output enable
inputs for enabling the respective differential outputs on the fly. The device
also features output enable control through I
2
C communication. I
2
C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for
free at www.silabs.com/pcie-learningcenter.
Functional Block Diagram
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock
compliant
Supports Serial ATA (SATA) at
100 MHz
100–210 MHz operation
Low power, push pull, differential
output buffers
Internal termination for maximum
integration
Dedicated output enable pin for
each clock
Two PCI-Express buffered clock
outputs
Supports LVDS outputs
I
2
C support with readback
capabilities
Extended temperature:
–40 to 85 °C
3.3 V Power supply
24-pin QFN package
Network attached storage
Multi-function Printer
Wireless access point
Routers
Control RAM
Control & Memory
DIFFIN
DIFFIN
SCLK
SDATA
OE [1:0]
DIFF0
DIFF1
Patents pending
Ordering Information:
See page 17
Pin Assignments
VDD
NC
VDD
VSS
VDD
OE_DIFF0*
VSS
DIFFIN
DIFFIN
1
2
3
4
5
6
24 23 22
21 20 19
7 8 9 10 11 12
18
17
16
15
14
13
NC
NC
NC
NC
NC
VDD
VDD
SDATA
SCLK
OE_DIFF1*
VDD
DIFF1
DIFF1
DIFF0
DIFF0
*Note: Internal 100 kohm pull-up.
25
GND
