Si53152
16 Rev. 1.2
16 DIFF1
O, DIF 0.7 V, 100 MHz differential clock.
17 VDD
PWR 3.3 V power supply.
18 OE_DIFF1
I,PU Active high input pin enables DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
19 SCLK
I SMBus compatible SCLOCK.
20 SDATA
I/O SMBus compatible SDATA.
21 VDD
PWR 3.3 V power supply.
22 DIFFIN
I 0.7 V Differential True Input, typically 100 MHz. Input frequency range
100 to 210 MHz.
23 DIFFIN
O 0.7 V Differential Complement Input, typically 100 MHz. Input frequency
range 100 to 210 MHz.
24 VSS
GND Ground.
25 GND GND Ground for bottom pad of the IC.
Table 6. Si53152 24-Pin QFN Descriptions (Continued)
Pin # Name Type Description
