Si53152
10 Rev. 1.2
4. Control Registers
4.1. I
2
C Interface
To enhance the flexibility and function of the clock buffer, an I
2
C interface is provided. Through the I
2
C Interface,
various device functions are available, such as individual clock output enable. The registers associated with the I
2
C
Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register
changes are normally made at system initialization, if any are required. Power management functions can only be
programed in program mode and not in normal operation modes.
4.2. Data Protocol
The I
2
C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block
write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller
can access individually indexed bytes.
The block write and block read protocol is outlined in Table 4 while Table 5 outlines byte write and byte read
protocol. The slave receiver address is 11010110 (D6h).
Table 4. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1
Start
1
Start
8:2
Slave address—7 bits
8:2
Slave address—7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code—8 bits
18:11
Command Code—8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count—8 bits
20
Repeat start
28
Acknowledge from slave
27:21
Slave address—7 bits
36:29
Data byte 1—8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
45:38
Data byte 2—8 bits
37:30
Byte Count from slave—8 bits
46
Acknowledge from slave
38
Acknowledge
....
Data Byte /Slave Acknowledges
46:39
Data byte 1 from slave—8 bits
....
Data Byte N—8 bits
47
Acknowledge
....
Acknowledge from slave
55:48
Data byte 2 from slave—8 bits
....
Stop
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
Si53152
Rev. 1.2 11
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1Start 1Start
8:2 Slave address–7 bits 8:2 Slave address–7 bits
9Write 9Write
10 Acknowledge from slave 10 Acknowledge from slave
18:11 Command Code–8 bits 18:11 Command Code–8 bits
19 Acknowledge from slave 19 Acknowledge from slave
27:20 Data byte–8 bits 20 Repeated start
28 Acknowledge from slave 27:21 Slave address–7 bits
29 Stop 28 Read
29 Acknowledge from slave
37:30 Data from slave–8 bits
38 NOT Acknowledge
39 Stop
Si53152
12 Rev. 1.2
Reset settings = 00000000
Reset settings = 00000000
Control Register 0. Byte 0
BitD7D6D5D4D3D2D1D0
Name
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:0 Reserved
Control Register 1. Byte 1
BitD7D6D5D4D3D2D1D0
Name
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:0 Reserved

SI53152-A01AGM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Buffer PCI-express Gen1/2/3 1:2 fan-out buffer
Lifecycle:
New from this manufacturer.
Delivery:
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