Si53152
Rev. 1.2 13
Reset settings = 11000000
Reset settings = 00001000
Reset settings = 00000110
Control Register 2. Byte 2
BitD7D6D5D4D3D2D1D0
Name
DIFF0_OE DIFF1_OE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 DIFF0_OE Output Enable for DIFF0.
0: Output disabled.
1: Output enabled.
6 DIFF1_OE Output Enable for DIFF1
0: Output disabled.
1: Output enabled.
5:0 Reserved
Control Register 3. Byte 3
BitD7D6D5D4D3D2D1D0
Name Rev Code[3:0] Vendor ID[3:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:4 Rev Code[3:0] Program Revision Code.
3:0
Vendor ID[3:0]
Vendor Identification Code.
Control Register 4. Byte 4
BitD7D6D5D4D3D2D1D0
Name BC[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:0 BC[7:0] Byte Count Register.
Si53152
14 Rev. 1.2
Reset settings = 11011000
Control Register 5. Byte 5
Bit D7 D6 D5 D4 D3D2D1D0
Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 DIFF_Amp_Sel Amplitude Control for DIFF Differential Outputs.
0: Differential outputs with Default amplitude.
1: Differential outputs amplitude is set by Byte 5[6:4].
6 DIFF_Amp_Cntl[2]
DIFF Differential Outputs Amplitude Adjustment.
000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV
100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV
5 DIFF_Amp_Cntl[1]
4 DIFF_Amp_Cntl[0]
3:0 Reserved
Si53152
Rev. 1.2 15
5. Pin Descriptions: 24-Pin QFN
Figure 4. 24-Pin QFN
Table 6. Si53152 24-Pin QFN Descriptions
Pin # Name Type Description
1VDD
PWR 3.3 V power supply.
2NC
NC No connect.
3VDD
PWR 3.3 V power supply.
4 VSS
GND Ground.
5OE_DIFF0
I,PU Active high input pin enables DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
6VDD
PWR 3.3 V power supply.
7NC
NC No connect.
8NC
NC No connect.
9NC
NC No connect.
10 NC
NC No connect.
11 NC
NC No connect.
12 VDD
PWR 3.3 V power supply.
13 DIFF0
O, DIF 0.7 V, 100 MHz differential clock.
14 DIFF0
O, DIF 0.7 V, 100 MHz differential clock.
15 DIFF1
O, DIF 0.7 V, 100 MHz differential clock.
VDD
NC
VDD
VSS
VDD
OE_DIFF0*
VSS
DIFFIN
DIFFIN
1
2
3
4
5
6
24 23 22
21 20 19
7 8 9 10 11 12
18
17
16
15
14
13
NC
NC
NC
NC
NC
VDD
VDD
SDATA
SCLK
OE_DIFF1*
VDD
DIFF1
DIFF1
DIFF0
DIFF0
*Note: Internal 100 kohm pull-up.
25
GND

SI53152-A01AGM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Buffer PCI-express Gen1/2/3 1:2 fan-out buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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