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DS1961S-F3+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
DS1961S
13 of 36
Figure 7-4. MEMORY AND SHA FUNCTIONS FLOW CHART (continued)
33h
Compute Next
Secret ?
Y
N
* 1-Wire Idle High for Power
Note
: The Master Must First
Load the Scratchpad With a
Partial Secret of 8 Bytes
From Figure 7
3rd Part
To Figure 7
3rd Part
From Figure 7
5th Part
To Figure 7
5th
Part
Valid Data
Address ?
Y
Bus Master
RX “1”s
Master
TX Reset ?
Y
N
N
N
SHA Engine Computes Message
Authentication Code of Current
Secret, Page Data, and 8 Byte
Partial Secret in Scratch
p
ad
DS1961S Copies a Partial
MAC to the Secret Re
g
ister
Master
TX Reset ?
Master
TX Reset ?
Y
N
DS1961S TX “1”
DS1961S TX “0”
N
Y
DS1961S Fills Scratch
p
ad With
A
Ah
*
*
Write-
Protected ?
Y
Bus Master TX
TA1
(
T7:T0
),
TA2
(
T15:T8
)
DS1961S Sets EN LFS = 0
Duration: t
CSHA
Duration: t
PROG
DS1961S
14 of 36
Figure 7-5. MEMORY AND SHA FUNCTIONS FLOW CHART (continued)
55h
Copy Scratch-
pad ?
Y
N
Bus Master TX
TA1 (T7:T0),
TA2 (T15:T8),
E/S B
y
te
Auth. Code
Match ?
N
Y
Bus Master
RX “1”s
Master
TX Reset ?
Y
N
A
A = 1
DS1961S Copies Scratch-
p
ad Data to Memor
y
Master
TX Reset ?
Master
TX Reset ?
Y
N
DS1961S TX “1”
DS1961S TX “0”
N
Y
MAC Code
Match ?
Y
N
N
DS1961S
TX “0”s
Master
TX Reset ?
Y
* 1-Wire Idle High for Power
SHA Engine Computes
Message Authentication
Code of Secret, 28 Bytes of
Page Data, Scratchpad
Data, and Device
Identit
y
Re
g
ister
Bus Master Computes MAC
and Sends it to DS1961S
*
*
From Figure 7
4th Part
To Figure 7
4th Part
To Figure 7
6th Part
From Figure 7
6th Part
Bus Master
Waits 10ms
Write-
Protected ?
Y
N
Note
: This Command is
A
pplicable to all R/W
Memor
y
Addresses.
Duration: t
CSHA
Duration: t
PROG
DS1961S
15 of 36
Figure 7-6. MEMORY AND SHA FUNCTIONS FLOW CHART (continued)
A5h
Read Auth.
Page ?
Y
N
* 1-Wire Idle High for Power
Note
: Three Bytes of the
Scratchpad Contents are Taken
as a Challenge to the DS1961S.
The Master can Specify the
Challenge or Accept the Current
Scratchpad Contents Instead.
Y
N
Address
< 80h ?
N
Bus Master
RX “1”s
Master
TX Reset ?
Y
DS1961S sets Memory
A
ddress =
(
T15:T0
)
Master
TX Reset ?
Y
N
Bus Master RX CRC16
of Command, Address,
Data
,
and FFh B
y
te
DS1961S
Increments
Address
Counter
Master
TX Reset ?
Master RX Data Byte
From Memor
y
Address
N
Y
End
Of Page ?
N
Y
Master RX
One B
y
te FFh
Master
TX Reset ?
Master
TX Reset ?
Y
N
DS1961S TX “1”
DS1961S TX “0”
N
Y
SHA Engine Computes
Message Authentication
Code of Secret, Data of
Selected Page, Device
Identity Register and
3-B
y
te Challen
g
e
Bus Master RX 160-Bit
Messa
g
e
A
uth. Code
Bus Master RX CRC16 of
Messa
g
e
A
uth. Code
*
From Figure 7
5th Part
To Figure 7
5th Part
To Figure 7
7th Part
From Figure 7
7th Part
Bus Master TX
TA1
(
T7:T0
),
TA2
(
T15:T8
)
DS1961S Sets EN
_
LFS = 0
Duration: t
CSHA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

DS1961S-F3+

Mfr. #:
Buy DS1961S-F3+
Manufacturer:
Maxim Integrated
Description:
iButtons & Accessories 1kb Protected EEPROM iButton w/SHA-1 Eng
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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