DS1961S
4 of 36
Figure 2. HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL
1-Wire Net
Other
Devices
Bus
Master
DS1961S
A
vailable
Commands:
Command
Level:
Data Field
A
ffected:
1-Wire ROM Function
Commands (See Figure 9)
DS1961S-Specific
Memory Function
Commands (See Figure 7)
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
64-bit Reg. #, RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag
Write Scratchpad
Read Scratchpad
Load First Secret
Compute Next Secret
Copy Scratchpad
Read Authenti-
cated Page
Read Memory
Refresh Scratchpad
64-bit Scratchpad, Flags
64-bit Scratchpad
Secret, Flags; Data Memory (after
Refresh Scratchpad)
Secret, Data Memory, Scratchpad
Data Memory or Register Page,
Secret, Flags, 64-Bit Reg. #,
Data Memory, Secret, 64-bit Reg. #,
3-Byte Challenge in Scratchpad
Data Memory, Register Page, Reg. #
64-bit Scratchpad, Data Memory,
Flags
Figure 3. 64-BIT LASERED ROM
MSB LSB
8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (33h)
MSB LSB MSB LSB MSB LSB
DS1961S
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Figure 4. 1-WIRE CRC GENERATOR
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
Pol
y
nomial = X
8
+ X
5
+ X
4
+ 1
1st
STAGE
2nd
STAGE
3rd
STAGE
4th
STAGE
6th
STAGE
5th
STAGE
7th
STAGE
8th
STAGE
INPUT DATA
MEMORY MAP
The DS1961S has four memory areas: data memory, secrets memory, register page with special function
registers and user-bytes, and a scratchpad. The data memory is organized in pages of 32 bytes. Secret,
register page, and scratchpad are 8 bytes each. The scratchpad acts as a buffer when writing to the data
memory, loading the initial secret or when writing to the register page.
Data memory, secrets memory, and the register page are located in a linear address space, as shown in
Figure 5. The data memory and the register page have unrestricted read access. Writing to the data
memory and the register page requires knowledge of the secret.
Figure 5. DS1961S MEMORY MAP
ADDRESS RANGE DESCRIPTION NOTE
0000h to 001Fh Data Memory Page 0 No Write-Access Without Secret
0020h to 003Fh Data Memory Page 1 No Write-Access Without Secret
0040h to 005Fh Data Memory Page 2 No Write-Access Without Secret
0060h to 007Fh Data Memory Page 3 No Write-Access Without Secret
0080h to 0087h Secrets Memory
No Read Access; No Secret Needed for
Write Access
0088h
1)
Write-Protect Secret, 008Ch to 008Fh Protection Activated by Code AAh or 55h
0089h
1)
Write-Protect Pages 0 to 3 Protection Activated by Code AAh or 55h
008Ah
1)
User Byte, Self-Protecting Protection Activated by Code AAh or 55h
008Bh Factory Byte (Read Only) Reads Either AAh or 55h; See Text
008Ch
1)
User Byte/EPROM Mode Control for
Page 1
Mode Activated by Code AAh or 55h
008Dh
1)
User Byte/Write-Protect Page 0 Only Protection Activated by Code AAh or 55h
008Eh to 008Fh User Bytes/Manufacturer ID Function Depends on Factory Byte
0090h to 0097h 64-Bit Identity Register Read-Only Access
1)
Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but
will neither write-protect the address nor activate any function.
DS1961S
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The secret can be installed either by copying data from the scratchpad to the secrets memory or by
computation using the current secret and the scratchpad contents as partial secret. The secret cannot be
read directly; only the SHA engine has access to it for computing message authentication codes.
The address range 0088h to 008Fh, also referred to as the Register Page, contains special function
registers as well as general-purpose user-bytes and one factory byte. Once programmed to AAh or 55h,
most of these bytes become write-protected and can no longer be altered. All other codes neither write-
protect the address nor activate the special function associated to that particular byte. Special functions
are: 1) write-protecting only the secret, 2) write-protecting all four data memory pages simultaneously, 3)
activating EPROM mode for data memory page 1 only, and 4) write-protecting data memory page 0 only.
Once EPROM mode is activated, bits in the address range 0020h through 003Fh can only be altered from
a logic 1 to a logic 0, provided that the data memory is not write protected.
The factory byte either reads 55H or AAh. Typically, this address reads 55h, indicating that the addresses
008E and 008F are read/write user-bytes without any special function or locking mechanism. The code of
AAh indicates that these two bytes are programmed with a 16-bit manufacturer ID and then write-
protected at the factory. The manufacturer ID can be a customer-supplied identification code that assists
the application software in identifying the product the DS1961S is associated with and in faster selection
of the applicable secret. To setup and register a manufacturer ID contact the factory.
The address range 0090h to 0097h is called the identity register. Typically, the identity register contains a
copy of the device’s ROM registration number. The family code is stored at the lower address followed
by the 48-bit serial number and the 8-bit CRC, which is stored at address 0097h. In reading through these
addresses (0090h to 0097h) the bus master receives the individual bits of the registration number in
exactly the same sequence as with a ROM function command. With customized versions, the content of
the identity register can be any customer-specified constant pattern. For more information on
customization contact the factory.
Figure 6. ADDRESS REGISTERS
Bit Number76543210
Target Address (TA1) T7 T6 T5 T4 T3
T2
(0)
T1
(0)
T0
(0)
Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8
Ending Address with
Data Status (E/S)
(Read Only)
AA 1 PF 1 1
E2
(1)
E1
(1)
E0
(1)
ADDRESS REGISTERS AND TRANSFER STATUS
The DS1961S employs three address registers: TA1, TA2, and E/S (Figure 6). These registers are
common to many other 1-Wire devices but operate slightly differently with the DS1961S. Registers TA1
and TA2 must be loaded with the target address to which the data is written or from which data is read.
Register E/S is a read-only transfer-status register, used to verify data integrity with write commands.
Since the scratchpad of the DS1961S is designed to accept data in blocks of eight bytes only, the lower
three bits of TA1 are forced to 0 and the lower three bits of the E/S register (ending offset) always read 1.

DS1961S-F3+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
iButtons & Accessories 1kb Protected EEPROM iButton w/SHA-1 Eng
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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