DS1961S-F3+ Datasheet DS1961S-F5+, DS1961S-F3+ | P22-P24

DS1961S

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After the master has issued the command code and specified the target addresses (TA1 and TA2), the

DS1961S first clears the EN_LFS flag. If the target address is valid (< 0080h), the master receives the

page data beginning at the target address through the end of the data page, one byte FFh and the inverted

CRC of the command code, target address, transmitted page data and FFh byte. If the target address is

invalid (³ 0080h), the master receives FFh bytes rather than page data. Immediately after the CRC is

received, the master waits for t

CSHA

during which the voltage on the 1-Wire bus must not fall below 2.8V.

During this time the SHA engine of the DS1961S computes the message authentication code over the

secret, all 32 data bytes of the selected page, the device’s registration number (without the CRC) and the

3-byte challenge. Now the master reads the 160-bit MAC, which is followed by an inverted CRC as a

means to safeguard the data transfer. If the master continues reading after the CRC it receives AAh.

Table 4. SHA-1 INPUT DATA FOR READ AUTHENTICATED PAGE COMMAND

M0[31:24] = (SS + 0) M0[23:16] = (SS + 1) M0[15:8] = (SS + 2) M0[7:0] = (SS + 3)

M1[31:24] = (PP + 0) M1[23:16] = (PP + 1) M1[15:8] = (PP + 2) M1[7:0] = (PP + 3)

M2[31:24] = (PP + 4) M2[23:16] = (PP + 5) M2[15:8] = (PP + 6) M2[7:0] = (PP + 7)

M3[31:24] = (PP + 8) M3[23:16] = (PP + 9) M3[15:8] = (PP + 10) M3[7:0] = (PP + 11)

M4[31:24] = (PP + 12) M4[23:16] = (PP + 13) M4[15:8] = (PP + 14) M4[7:0] = (PP + 15)

M5[31:24] = (PP + 16) M5[23:16] = (PP + 17) M5[15:8] = (PP + 18) M5[7:0] = (PP + 19)

M6[31:24] = (PP + 20) M6[23:16] = (PP + 21) M6[15:8] = (PP + 22) M6[7:0] = (PP + 23)

M7[31:24] = (PP + 24) M7[23:16] = (PP + 25) M7[15:8] = (PP + 26) M7[7:0] = (PP + 27)

M8[31:24] = (PP + 28) M8[23:16] = (PP + 29) M8[15:8] = (PP + 30) M8[7:0] = (PP + 31)

M9[31:24] = FFh M9[23:16] = FFh M9[15:8] = FFh M9[7:0] = FFh

M10[31:24] = MP M10[23:16] = (ID + 0) M10[15:8] = (ID + 1) M10[7:0] = (ID + 2)

M11[31:24] = (ID + 3) M11[23:16] = (ID + 4) M11[15:8] = (ID + 5) M11[7:0] = (ID + 6)

M12[31:24] = (SS + 4) M12[23:16] = (SS + 5) M12[15:8] = (SS + 6) M12[7:0] = (SS + 7)

M13[31:24] = (SP + 4) M13[23:16] = (SP + 5) M13[15:8] = (SP + 6) M13[7:0] = 80h

M14[31:24] = 00h M14[23:16] = 00h M14[15:8] = 00h M14[7:0] = 00h

M15[31:24] = 00h M15[23:16] = 00h M15[15:8] = 01h M15[7:0] = B8h

Legend

Mt Input Buffer of SHA Engine

0 £ t £ 15; 32-Bit Words

(SS + N) Byte N of Secret; Secret Begins at Address 0080h

(See Memory Map)

(PP + N) Byte N of Memory Page; Memory Pages Begin at

0000h, 0020h, 0040h and 0060h (see Memory Map)

(SP + N) Byte N of Scratchpad

MP[7:3] = 01000b,

MP[2:0] = T7:T5

(ID + N) Byte N of Identity Register

The Last Byte of the Identity Register is Not Used.

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Refresh Scratchpad [A3h]

Refresh scratchpad loads memory data to the scratchpad and sets the EN_LFS flag, which enables the use

of the load first secret command to re-write the data that was just read from the memory, bypassing the

MAC computation of copy scratchpad.

The command flow chart of refresh scratchpad is very similar to write scratchpad. If the target address is

between 0000h–007Fh, there are two primary differences. 1) The data bytes that the master transmits

following the target address are discarded; instead, the scratchpad is loaded with the unaltered memory

data located at the target address, even if the memory page is in EPROM mode. 2) After the master has

transmitted the eight dummy bytes, the EN_LFS flag is set to 1. The EN_LFS flag is cleared to 0 after

receiving TA1 and TA2 during a write scratchpad, compute next secret, read authenticated page, refresh

scratch, read memory, or by a power-on reset, because these commands can change the target address

and/or the data in the scratchpad.

When applied to addresses 0080h–008Fh, the refresh scratchpad command behaves the same way as

write scratchpad. This protects the secret from being exposed by a subsequent read scratchpad command.

Read Memory [F0h]

The read memory command can be used to read all memory except for the secret. Attempting to read the

secret results in FFh bytes instead of the actual secret. After the master has issued the command code and

specified the target addresses (TA1 and TA2), the DS1961S first clears the EN_LFS flag. If the target

address is valid, the master reads data beginning from the target address and can continue until address

0097h. If the master continues reading, the result is logic 1s. It is important to realize that the target

address registers point to the last byte read. The ending offset/data status byte and the scratchpad are

unaffected.

The hardware of the DS1961S provides a means to accomplish error-free writing to the memory section.

To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is

recommended to packetize data into data packets of the size of one memory page each. Such a packet

typically stores a master-calculated 16-bit CRC with each page of data to ensure rapid, error-free data

transfers that eliminate having to read a page multiple times to determine if the received data is correct or

not. (Refer to Application Note 114 for the recommended file structure, which is also referred to as

TMEX Format.)

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SHA-1 COMPUTATION ALGORITHM

This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document

that can be downloaded from the NIST website (www.itl.nist.gov/fipspubs/fip180-1.htm). The algorithm

takes as its input data sixteen 32-bit words M

(0 £ t £ 15), as shown in Tables 1, 3A, 3B, and 4 for the

compute next secret, copy scratchpad, and read authenticated page command, respectively. The SHA

computation involves a sequence of eighty 32-bit words called W

(0 £ t £ 79), a sequence of eighty 32-

bit words called K

(0 £ t £ 79), a Boolean function f

(B, C, D) (0 £ t £ 79) with B, C, and D being 32-bit

words, and three more 32-bit words called A, E, and TMP. The operations required for the SHA

computation are arithmetic addition without carry (“+”), logical inversion or 1’s complement (“\”),

EXCLUSIVE OR (“Å”), logical AND (“Ù”), logical OR (“Ú”), assignment (“:=”), and circular shifting

within a 32-bit word. The expression “S

(X)” represents a circular shift of X by n positions to the left,

with X being a 32-bit word.

The function f

is defined as follows:

(B,C,D) = (B Ù C) Ú ((B\) Ù D) (0 £ t £ 19)

B Å C Å D (20 £ t £ 39)

(B Ù C) Ú (B Ù D) Ú (C Ù D) (40 £ t £ 59)

B Å C Å D (60 £ t £ 79)

The sequence W

(0 £ t £ 79) is defined as follows:

:= M

(0 £ t £ 15)

t-3

Å W

t-8

Å W

t-14

Å W

t-16

) (16 £ t £ 79)

The sequence K

(0 £ t £ 79) is defined as follows:

:= 5A827999h (0 £ t £ 19)

6ED9EBA1h (20 £ t £ 39)

8F1BBCDCh (40 £ t £ 59)

CA62C1D6h (60 £ t £ 79)

The variables A, B, C, D, E are initialized as follows:

A := 67452301h

B := EFCDAB89h

C := 98BADCFEh

D := 10325476h

E:= C3D2E1F0h

The 160-bit MAC is the concatenation of A, B, C, D, and E after looping through the following set of

computations for t = 0 to 79 (discarding any carry-out):

TMP := S

(A) + f

(B,C,D) + W

+ K

+ E

E:= D

D:= C

C:= S

(B)

B:= A

A:= TMP

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DS1961S-F3+

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iButtons & Accessories 1kb Protected EEPROM iButton w/SHA-1 Eng

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DS1961S-F3+

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