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70V631S12PRF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(5)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual t
DH will always be smaller than the actual tOW.
5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
Symbol Parameter
70V631S10
Com'l Only
70V631S12
Com'l
& Ind
70V631S15
Com'l
UnitMin. Max. Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15 ns
t
ACE
Chip Enable Access Time
(3)
____
10
____
12
____
15 ns
t
ABE
Byte Enable Access Time
(3)
____
5
____
6
____
7ns
t
AOE
Output Enable Access Time
____
5
____
6
____
7ns
t
OH
Output Hold from Address Change 3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
040608ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
10
____
10
____
15 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)
____
4
____
6
____
8ns
t
SAA
Semaphore Address Access Time 3 10 3 12 3 20 ns
5622 tbl 12
Symbol Parameter
70V631S10
Com'l Only
70V631S12
Com'l
& Ind
70V631S15
Com'l
UnitMin. Max. Min. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 10
____
12
____
15
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
8
____
10
____
12
____
ns
t
AW
Address Valid to End-of-Write 8
____
10
____
12
____
ns
t
AS
Address Set-up Time
(3 )
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 8
____
10
____
12
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write 6
____
8
____
10
____
ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
4
____
4
____
4ns
t
OW
Output Active from End-of-Write
(1, 2 ,4)
0
____
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
5622 tbl 13
11
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first CE, OE, LB or UB.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
t
RC
R/W
CE
ADDR
t
AA
OE
UB, LB
5622 drw 06
(4)
t
ACE
(4)
t
AOE
(4)
t
ABE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
(6)
CE
5622 drw 07
t
PU
I
CC
I
SB
t
PD
50% 50%
.
IDT70V631S
High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
12
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1,5)
NOTES:
1. R/W or CE or BEn = V
IH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V
IL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = V
IL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP.
9. To access RAM, CE = V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4) (4)
(7)
UB, LB
5622 drw 08
(9)
CE or SEM
(9)
(7)
(3)
5622 drw 09
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
UB, LB
(3)
(2)
(6)
CE or SEM
(9)
(9)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

70V631S12PRF8

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Buy 70V631S12PRF8
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Description:
SRAM 256Kx18 STD-PWR 3.3V DUAL-PORT RAM
Lifecycle:
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