70V631S12PRF8 Datasheet 70V631S10BFG, 70V631S12PRFGI, 70V631S10BCG8 | P4-P6

IDT70V631S

High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

4

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:

1. All V

DD pins must be connected to 3.3V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V

IL (0V).

3. All V

SS pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

70V631BC

BC-256

(5)

256-Pin BGA

Top View

(6)

E16

I/O

7R

D16

I/O

8R

C16

I/O

8L

B16

NC

A16

NC

A15

NC

B15

NC

C15

NC

D15

NC

E15

I/O

7L

E14

NC

D14

NC

D13

V

DD

C12

A

6L

C14

OPT

L

B14

NC

A14

A

0L

A12

A

5L

B12

A

4L

C11

BUSY

L

D12

V

DDQR

D11

V

DDQR

C10

SEM

L

B11

NC

A11

INT

L

D8

V

DDQR

C8

NC

A9

CE

1L

D9

V

DDQL

C9

LB

L

B9

CE

0L

D10

V

DDQL

C7

A

7L

B8

UB

L

A8

NC

B13

A

1L

A13

A

2L

A10

OE

L

D7

V

DDQR

B7

A

9L

A7

A

8L

B6

A

12L

C6

A

10L

D6

V

DDQL

A5

A

14L

B5

A

15L

C5

A

13L

D5

V

DDQL

A4

A

17L

B4

NC

C4

A

16L

D4

V

DD

A3

NC

B3

TDO

C3

V

SS

D3

NC

D2

I/O

9R

C2

I/O

9L

B2

NC

A2

TDI

A1

NC

B1

NC

C1

NC

D1

NC

E1

I/O

10R

E2

I/O

10L

E3

NC

E4

V

DDQL

F1

I/O

11L

F2

NC

F3

I/O

11R

F4

V

DDQL

G1

NC

G2

NC

G3

I/O

12L

G4

V

DDQR

H1

NC

H2

I/O

12R

H3

NC

H4

V

DDQR

J1

I/O

13L

J2

I/O

14R

J3

I/O

13R

J4

V

DDQL

K1

NC

K2

NC

K3

I/O

14L

K4

V

DDQL

L1

I/O

15L

L2

NC

L3

I/O

15R

L4

V

DDQR

M1

I/O

16R

M2

I/O

16L

M3

NC

M4

V

DDQR

N1

NC

N2

I/O

17R

N3

NC

N4

V

DD

P1

NC

P2

I/O

17L

P3

TMS

P4

A

16R

R1

NC

R2

NC

R3

TRST

R4

NC

T1

NC

T2

TCK

T3

NC

T4

A

17R

P5

A

13R

R5

A

15R

P12

A

6R

P8

NC

P9

LB

R

R8

UB

R

T8

NC

P10

SEM

R

T11

INT

R

P11

BUSY

R

R12

A

4R

T12

A

5R

P13

A

3R

P7

A

7R

R13

A

1R

T13

A

2R

R6

A

12R

T5

A

14R

T14

A

0R

R14

OPT

R

P14

NC

P15

NC

R15

NC

T15

NC

T16

NC

R16

NC

P16

I/O

0L

N16

NC

N15

I/O

0R

N14

NC

M16

NC

M15

I/O

1L

M14

I/O

1R

L16

I/O

2R

L15

NC

L14

I/O

2L

K16

I/O

3L

K15

NC

K14

NC

J16

I/O

4L

J15

I/O

3R

J14

I/O

4R

H16

I/O

5R

H15

NC

H14

NC

G16

NC

G15

NC

G14

I/O

5L

F16

I/O

6L

F14

I/O

6R

F15

NC

R9

CE

0R

R11

M/S

T6

A

11R

T9

CE

1R

A6

A

11L

B10

R/W

L

C13

A

3L

P6

A

10R

R10

R/W

R

R7

A

9R

T10

OE

R

T7

A

8R

,

E5

V

DD

E6

V

DD

E7

V

SS

E8

V

SS

E9

V

SS

E10

V

SS

E11

V

DD

E12

V

DD

E13

V

DDQR

F5

V

DD

F6

V

SS

F8

V

SS

F9

V

SS

F10

V

SS

F12

V

DD

F13

V

DDQR

G5

V

SS

G6

V

SS

G7

V

SS

G8

V

SS

G9

V

SS

G10

V

SS

G11

V

SS

G12

V

SS

G13

V

DDQL

H5

V

SS

H6

V

SS

H7

V

SS

H8

V

SS

H9

V

SS

H10

V

SS

H11

V

SS

H12

V

SS

H13

V

DDQL

J5

V

SS

J6

V

SS

J7

V

SS

J8

V

SS

J9

V

SS

J10

V

SS

J11

V

SS

J12

V

SS

J13

V

DDQR

K5

V

SS

K6

V

SS

K7

V

SS

K8

V

SS

L5

V

DD

L6

V

SS

L7

V

SS

L8

V

SS

M5

V

DD

M6

V

DD

M7

V

SS

M8

V

SS

N5

V

DDQR

N6

V

DDQR

N7

V

DDQL

N8

V

DDQL

K9

V

SS

K10

V

SS

K11

V

SS

K12

V

SS

L9

V

SS

L10

V

SS

L11

V

SS

L12

V

DD

M9

V

SS

M10

V

SS

M11

V

DD

M12

V

DD

N9

V

DDQR

N10

V

DDQR

N11

V

DDQL

N12

V

DDQL

K13

V

DDQR

L13

V

DDQL

M13

V

DDQL

N13

V

DD

F7

V

SS

F11

V

SS

5622 drw 02c

,

09/30/03

5

IDT70V631S

High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

NOTES:

1. V

DD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/O

X.

2. OPT

X selects the operating voltage levels for the I/Os and controls on that port.

If OPT

X is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and controls will operate at 2.5V levels and V

DDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

Left Port Right Port Names

CE

0L

,

CE

1L

CE

0R

,

CE

1R

Chip Enables

R/W

L

R/W

R

Read/Write Enable

OE

L

OE

R

Output Enable

A

0L

- A

17L

A

0R

- A

17R

Address

I/O

0L

- I/O

17L

I/O

0R

- I/O

17R

Data Input/Output

SEM

L

SEM

R

Semaphore Enable

INT

L

INT

R

Interrupt Flag

BUSY

L

BUSY

R

Busy Flag

UB

L

UB

R

Upper Byte Select

LB

L

LB

R

Lower Byte Select

V

DD Q L

V

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(1)

OPT

L

OPT

R

Option for selecting V

DDQX

(1,2)

M/S Master or Slave Select

V

DD

Power (3.3V)

(1 )

V

SS

Ground (0V)

TDI Test Data Input

TDO Test Data Output

TCK Test Logic Clock (10MHz)

TMS Test Mode Select

TRST

Reset (Initialize TAP Controller)

5622 tbl 01

IDT70V631S

High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

6

NOTE:

1. "H" = V

IH, "L" = VIL, "X" = Don't Care.

Truth Table I—Read/Write and Enable Control

(1)

OE SEM CE

0

CE

1

UB LB

R/W

Byte 1

I/O

9-17

Byte 0

I/O

0-8

MODE

X H H X X X X High-Z High-Z Deselected–Power Down

X H X L X X X High-Z High-Z Deselected–Power Down

X H L H H H X High-Z High-Z Both Bytes Deselected

XHLHHLLHigh-Z D

IN

Write to Byte 0 Only

XHLHLHL D

IN

High-Z Write to Byte 1 Only

XHLHLLL D

IN

D

IN

Write to Both Bytes

LHLHHLHHigh-ZD

OUT

Read Byte 0 Only

LHLHLHHD

OUT

High-Z Read Byte 1 Only

LHLHLLHD

OUT

D

OUT

Read Both Bytes

H H L H L L X High-Z High-Z Outputs Disabled

5622 tbl 02

Truth Table II – Semaphore Read/Write Control

(1)

NOTE:

1. There are eight semaphore flags written to I/O

0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2.

2. CE = L occurs when CE

0 = VIL and CE1 = VIH.

3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = V

IL.

Inputs

(1 )

Outputs

Mode

CE

R/W

OE UB LB SEM

I/O

1-17

I/O

0

HHLLLLDATA

OUT

DATA

OUT

Read Data in Semaphore Flag

(3 )

H

↑

XXL L X DATA

IN

Write I/O

0

into Semaphore Flag

LXXXX L

______ ______

Not Allowed

5622 tbl 03

70V631S12PRF8

70V631S12PRF8

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