CAT28F001
10
Doc. No. MD-1078, Rev. K
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
When the Status Register indicates that programming is
complete, the Program Status bit should be checked. If
program error is detected, the Status Register should be
cleared. The internal WSM verify only detects errors for
“1s” that do not successfully program to “0s”. The
Command Register remains in Read Status Register
mode until further commands are issued to it.
If erase/byte program is attempted while V
PP
= V
PPL
, the
Status bit (SR.5/SR.4) will be set to “1”. Erase/Program
attempts while V
PPL
< V
PP
< V
PPH
produce spurious
results and should not be attempted.
EMBEDDED ALGORITHMS
The CAT28F001 integrates the Quick Pulse program-
ming algorithm on-chip, using the Command Register,
Status Register and Write State Machine (WSM). On-
chip integration dramatically simplifies system software
and provides processor-like interface timings to the
Command and Status Registers. WSM operation, inter-
nal program verify, and V
PP
high voltage presence are
monitored and reported via appropriate Status Register
bits. Figure 4 shows a system software flowchart for
device programming.
As above, the Quick Erase algorithm is now imple-
mented internally, including all preconditioning of block
data. WSM operation, erase verify and V
PP
high voltage
presence are monitored and reported through the Status
Register. Additionally, if a command other than Erase
Confirm is written to the device after Erase Setup has
been written, both the Erase Status and Program Status
bits will be set to “1”. When issuing the Erase Setup and
Erase Confirm commands, they should be written to an
address within the address range of the block to be
erased. Figure 5 shows a system software flowchart for
block erase.
The entire sequence is performed with V
PP
at V
PPH
.
Abort occurs when RP transitions to V
IL
, or V
PP
drops to
V
PPL
. Although the WSM is halted, byte data is partially
programmed or Block data is partially erased at the
location where it was aborted. Block erasure or a repeat
of byte programming will initialize this data to a known
value.
BOOT BLOCK PROGRAM AND ERASE
The boot block is intended to contain secure code which
will minimally bring up a system and control program-
ming and erase of other blocks of the device, if needed.
Therefore, additional “lockout” protection is provided to
guarantee data integrity. Boot block program and erase
operations are enabled through high voltage V
HH
on
either RP or OE, and the normal program and erase
command sequences are used. Reference the AC
Waveforms for Program/Erase.
If boot block program or erase is attempted while RP is
at V
IH
, either the Program Status or Erase Status bit will
be set to “1”, reflective of the operation being attempted
and indicating boot block lock. Program/erase attempts
while V
IH
< RP < V
HH
produce spurious results and
should not be attempted.
NOTES:
The Write State Machine Status Bit must first be checked to
determine program or erase completion, before the
Program or Erase Status bits are checked for success.
If the Program AND Erase Status bits are set to “1s” during an
erase attempt, an improper command sequence was
entered. Attempt the operation again.
If V
PP
low status is detected, the Status Register must be
cleared before another program or erase operation is
attempted.
The V
PP
Status bit, unlike an A/D converter, does not provide
continuous indication of V
PP
level. The WSM interrogates
the V
PP
level only after the program or erase command
sequences have been entered and informs the system if
V
PP
has not been switched on. The V
PP
Status bit is not
guaranteed to report accurate feedback between V
PPL
and
V
PPH
.
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
0 = Erase in Progress/Completed
SR.5 = ERASE STATUS
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = PROGRAM STATUS
1 = Error in Byte Program
0 = Successful Byte Program
SR.3 = VPP STATUS
1 = V
PP
Low Detect; Operation Abort
0 = V
PP
Okay
SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked
out when polling the Status Register.
WSMS ESS ES PS VPPS R R R
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