CAT28F001H-12T Datasheet CAT28F001G-12T, CAT28F001GI-12TT, CAT28F001G-90B | P7-P9

CAT28F001

Doc. No. MD-1078, Rev. K

Characteristics subject to change without notice

ERASE AND PROGRAMMING PERFORMANCE

FUNCTION TABLE

(1)

Pins

Mode

RPRP

CECE

OEOE

WEWE

WE V

I/O Notes

Read V

OUT

Output Disable V

X High-Z

Standby V

X X X High-Z

Signature (MFG) V

X 31H A

= V

, A

= 12V

Signature (Device) V

X 94H-28F001T A

= V

, A

= 12V

95H-28F001B

Write Cycle V

During Write Cycle

Deep Power Down V

XXXXHIGH-Z

WRITE COMMAND TABLE

Commands are written into the command register in one or two write cycles. Write cycles also internally latch

addresses and data required for programming and erase operations.

First Bus Cycle Second Bus Cycle

Mode Operation Address D

Operation Address D

OUT

Read Array/Reset Write X FFH

Program Setup/ Write A

40H Write A

Program 10H

Read Status Reg. Write X 70H Read X St. Reg. Data

Clear Status Reg. Write X 50H

Erase Setup/Erase Write Block ad 20H Write Block ad D0H

Confirm

Erase Suspend/ Write X B0H Write X D0H

Erase Resume

Read Sig (Mfg) Write X 90H Read 0000H 31H

Read Sig (Dev) Write X 90H Read 0001H 94H-28F001T

95H-28F001B

Note:

(1) Logic Levels: X = Logic ‘Do not care’ (V

, V

PPL

, V

PPH

)

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CAT28F001

Doc. No. MD-1078, Rev. K

Characteristics subject to change without notice

READ OPERATIONS

Read Mode

The CAT28F001 memory can be read from any of its

Blocks (Boot Block, Main Block or Parameter Block),

Status Register and Signature Information by sending

the Read Command Mode to the Command Register.

CAT28F001 automatically resets to Read Array mode

upon initial device power up or after exit from deep

power down. A Read operation is performed with both

CE and OE low and with RP and OE high. Vpp can be

either high or low. The data retrieved from the I/O pins

reflects the contents of the memory location correspond-

ing to the state of the 17 address pins. The respective

timing waveforms for the read operation are shown in

Figure 3. Refer to the AC Read characteristics for

specific timing parameters.

Signature Mode

The signature mode allows the user to identify the IC

manufacturer and the type of the device while the device

resides in the target system. This mode can be activated

in either of two ways; through the conventional method

of applying a high voltage (12V) to address pin A9 or by

sending an instruction to the command register (see

Write Operations).

The conventional method is entered as a regular read

mode by driving the CE and OE low (with WE high), and

applying the required high voltage on address pin A9

while the other address line are held at VIL.

A Read cycle from address 0000H retrieves the binary

code for the IC manufacturer on outputs I/O

to I/O

Catalyst Code = 0011 0001 (31H)

A Read cycle from address 0001H retrieves the binary

code for the device on outputs I/O

to I/O

CAT28F001T = 1001 0100 (94H)

CAT28F001B = 1001 0101 (95H)

Standby Mode

With CE at a logic-high level, the CAT28F001 is placed

in a standby mode where most of the device circuitry is

disabled, thereby substantially reducing power con-

sumption. The outputs are placed in a high-impendance

state independent of the OE status.

Deep Power-Down

When RP is at logic-low level, the CAT28F001 is placed

in a Deep Power-Down mode where all the device

circuitry are disabled, thereby reducing the power con-

sumption to 0.25µW.

Figure 3. A.C. Timing for Read Operation

ADDRESSES

CE (E)

OE (G)

WE (W)

DATA (I/O)

HIGH-Z

POWER UP

STANDBY DEVICE AND

ADDRESS SELECTION

OUPUTS

ENABLED

DATA VALID STANDBY

ADDRESS STABLE

OUTPUT VALID

AVQV

ACC

)

ELQX

)

GLQX

OLZ

)

GLQV

)

ELQV

)

GHQZ

)

EHQZ

AVAV

)

POWER DOWN

HIGH-Z

PHQV

PWH

)

RP (P)

CAT28F001

Doc. No. MD-1078, Rev. K

Characteristics subject to change without notice

WRITE OPERATIONS

The following operations are initiated by observing the

sequence specified in the Write Command Table.

Read Array

The device can be put into a Read Array Mode by

initiating a write cycle with FFH on the data bus. The

device is also in a standard Read Array Mode after the

initial device power up and when comes out of the Deep

Power-Down mode.

Signature Mode

An alternative method for reading device signature (see

Read Operations Signature Mode), is initiated by writing

the code 90H into the command register. A read cycle

from address 0000H with CE and OE low (and WE high)

will output the device signature.

Catalyst Code = Catalyst Code = 0011 0001 (31H)

A Read cycle from address 0001H retrieves the

binary code for the device on outputs I/O

to I/O

CAT28F001T = 1001 0100 (94H)

CAT28F001B = 1001 0101 (95H)

To terminate the operations, it is necessary to write

another valid command into the register.

STATUS REGISTER

The 28F001 contains an 8-bit Status Register. The

Status Register is polled to check for write or erase

completion or any related errors. The Status Register

may be read at any time by issuing a Read Status

tions output data from the Status Register, until another

valid command is issued. The contents of the Status

whichever occurs last in the read cycle. OE or CE must

be toggled to VIH before further reads to update the

status register latch.

The Erase Status (SR.5) and Program Status (SR.4) are

set to 1 by the WSM and can only be reset issuing Clear

Status Register (50H) These two bits can be polled for

failures, thus allowing more flexibility to the designer

when using the CAT28F001. Also, VPP Status (SR.3)

when set to 1 must be reset by system software before

any further byte programs or block erases are attempted.

ERASE SETUP/ERASE CONFIRM

Erase is executed one block at a time, initiated by a two

cycle command sequence. The two cycle command

sequence provides added security against accidental

block erasure. During the first write cycle, a Command

20H (Erase Setup) is first written to the Command

firm). These commands require both appropriate com-

mand data and an address within Block to be erased.

Also, Block erasure can only occur when VPP= VPPH.

Block preconditioning, erase and verify are all handled

internally by the Write State Machine, invisible to the

system. After receiving the two command erase se-

quence the CAT28F001 automatically outputs Status

the completion of the erase event by checking if the

SR.7 of the Status Register is set.

SR.5 will indicate whether the erase was successful. If

an erase error is detected, the Status Register should be

cleared. The device will be in the Status Register Read

Mode until another command is issued.

ERASE SUSPEND/ERASE RESUME

The Erase Suspend Command allows erase sequence

interruption in order to read data from another block of

memory. Once the erase sequence is started, writing

the Erase Suspend command (B0H) to the Command

sequence at a predetermined point in the erase algo-

rithm. The CAT28F001 continues to output Status Reg-

ister data when read, after the Erase Suspend command

is written to it. Polling the WSM Status and Erase

Suspend Status bits will determine when the erase

operation has been suspended (both will be set to “1s”).

The device may now be given a Read ARRAY Com-

mand, which allows any locations 'not within the block

being erased' to be read. Also, you can either perform

a Read Status Register or resume the Erase Operation

by sending Erase Resume (D0H), at which time the

WSM will continue with the erase sequence. The Erase

Suspend Status and WSM Status bits of the Status

PROGRAM SETUP/PROGRAM COMMANDS

Programming is executed by a two-write sequence. The

program Setup command (40H) is written to the Com-

mand Register, followed by a second write specifying

the address and data (latched on the rising edge of WE)

to be programmed. The WSM then takes over, control-

ling the program and verify algorithms internally. After

the two-command program sequence is written to it, the

CAT28F001 automatically outputs Status Register data

when read (see figure 4; Byte Program Flowchart). The

CPU can detect the completion of the program event by

analyzing the WSM Status bit of the Status Register.

Only the Read Status Register Command is valid while

programming is active.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

CAT28F001H-12T

Mfr. #:

Buy CAT28F001H-12T

Manufacturer:

ON Semiconductor

Description:

IC FLASH 1M PARALLEL 32TSOP

Lifecycle:

New from this manufacturer.

Delivery:

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CAT28F001H-12T

CAT28F001H-12T

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